GICR0_FCTLR

         GICR0_FCTLR


Module Instance	Base Address	Register Address
`i_aps_gic__gic_axi4_slave__1d000000__GICRlpi0`	`0x1D060000`	`0x1D060020`

Size: 32

Offset: 0x20

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`QD` `RW 0x0`	`RESERVED1` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RESERVED1` `RW 0x0`									`CGO` `RW 0x0`			`RESERVED0` `RW 0x0`			`SIP` `RW 0x0`

GICR0_FCTLR Fields


Bit	Name	Description	Access	Reset
31	`QD`	QD	`RW`	`0x0`
30:7	`RESERVED1`	RESERVED1	`RW`	`0x0`
6:4	`CGO`	CGO	`RW`	`0x0`
3:1	`RESERVED0`	RESERVED0	`RW`	`0x0`
0	`SIP`	SIP	`RW`	`0x0`