INTMODE 

         Interrupt modes of ECC RAM system
Module Instance Base Address Register Address
ecc_qspi__ecc_csr__10a22000__ecc_registerBlock__SEG_hps2sdm_be_0x220000_0x10000 0x10A22000 0x10A2201C - 0x10A22074

Size: 32

Offset: 0x1C

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_3

RO 0x0

INTONCMP

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_2

RO 0x0

INTONOVF

RW 0x0

Reserved_1

RO 0x0

INTMODE

RW 0x0

INTMODE Fields

Bit Name Description Access Reset
31:17 Reserved_3 
Reserved bitfield added by Magillem
 RO 0x0
16 INTONCMP 
Enable interrupt on compare.
Value Description
0 Disable interrupt on compare feature
1 Enable interrupt on compare feature
RW 0x0
15:9 Reserved_2 
Reserved bitfield added by Magillem
 RO 0x0
8 INTONOVF 
Enable interrupt on overflow.
Value Description
0 Disable interrupt on LUT overflow
1 Enable interrupt on LUT overflow
RW 0x0
7:1 Reserved_1 
Reserved bitfield added by Magillem
 RO 0x0
0 INTMODE 
Interrupt mode for single-bit error
Value Description
0 Enable interrupt on all error mode. Every single-bit error will cause interrupt.
1 Enable interrupt on distinct error. Every distinct error which is logged into LUT will cause interrupt.
RW 0x0