ECC_WDataecc1bus

         The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved.


Module Instance	Base Address	Register Address
`ecc_qspi__ecc_csr__10a22000__ecc_registerBlock__SEG_hps2sdm_be_0x220000_0x10000`	`0x10A22000`	`0x10A22070 - 0x10A2215E`

Size: 32

Offset: 0x70

Access: WO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`ECC_WDataecc7BUS` `WO 0x0`								`ECC_WDataecc6BUS` `WO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`ECC_WDataecc5BUS` `WO 0x0`								`ECC_WDataecc4BUS` `WO 0x0`

ECC_WDataecc1bus Fields


Bit	Name	Description	Access	Reset
31:24	`ECC_WDataecc7BUS`	Eccdata from the register will be written to the RAM.	`WO`	`0x0`
23:16	`ECC_WDataecc6BUS`	Eccdata from the register will be written to the RAM.	`WO`	`0x0`
15:8	`ECC_WDataecc5BUS`	Eccdata from the register will be written to the RAM.	`WO`	`0x0`
7:0	`ECC_WDataecc4BUS`	Eccdata from the register will be written to the RAM.	`WO`	`0x0`