CTRL 

         ECC Control Register
Module Instance Base Address Register Address
ecc_qspi__ecc_csr__10a22000__ecc_registerBlock__SEG_hps2sdm_be_0x220000_0x10000 0x10A22000 0x10A22008 - 0x10A22054

Size: 32

Offset: 0x8

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_6

RO 0x0

INITB

RW 0x0

Reserved_5

RO 0x0

INITA

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_4

RO 0x0

CNT_RSTB

RW 0x0

CNT_RSTA

RW 0x0

Reserved_2

RO 0x0

ECC_SLVERR_DIS

RW 0x1

ECC_EN

RW 0x0

CTRL Fields

Bit Name Description Access Reset
31:25 Reserved_6 
Reserved bitfield added by Magillem
 RO 0x0
24 INITB 
Start for the hardware memory initialization PORTB.
 RW 0x0
23:17 Reserved_5 
Reserved bitfield added by Magillem
 RO 0x0
16 INITA 
Start for the hardware memory initialization PORTA.
 RW 0x0
15:10 Reserved_4 
Reserved bitfield added by Magillem
 RO 0x0
9 CNT_RSTB 
Clear internal single-bit error counter B value to zero
 RW 0x0
8 CNT_RSTA 
Clear internal single-bit error counter A value to zero
 RW 0x0
7:2 Reserved_2 
Reserved bitfield added by Magillem
 RO 0x0
1 ECC_SLVERR_DIS 
Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface.
Value Description
0 DISABLE
1 ENABLE
RW 0x1
0 ECC_EN 
Enable for the ECC detection and correction logic.
Value Description
0 DISABLE
1 ENABLE
RW 0x0