TFR

         Transmit FIFO Read


Module Instance	Base Address	Register Address
`i_uart__uart_csr__108d0000__uart_address_block__SEG_hps2sdm_be_0x0_0x400`	`0x108D0000`	`0x108D0074`

Size: 32

Offset: 0x74

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RSVD_TFR_31to8` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RSVD_TFR_31to8` `RO 0x0`								`tfr` `RO 0x0`

TFR Fields

Bit Name Description Access Reset

31:8

Bit	Name	Description	Access	Reset
31:8	`RSVD_TFR_31to8`	Reserved bits [31:8] - Read Only	`RO`	`0x0`
7:0	`tfr`	Transmit FIFO Read. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFO's are implemented and enabled, reading this register gives the data at the top of the transmit FIFO. Each consecutive read pops the transmit FIFO and gives the next data value that is currently at the top of the FIFO. When FIFO's are not implemented or not enabled, reading this register gives the data in the THR.	`RO`	`0x0`

RSVD_TFR_31to8

Reserved bits [31:8] - Read Only

RO

0x0

7:0

tfr

Transmit FIFO Read.
These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one).
When FIFO's are implemented and enabled, reading this register gives the data at the
top of the transmit FIFO. Each consecutive read pops the transmit FIFO and gives the
next data value that is currently at the top of the FIFO.
When FIFO's are not implemented or not enabled, reading this register gives the data
in the THR.

RO

0x0