MODSTAT

         <p>Mode status flag</p>


Module Instance	Base Address	Register Address
`i_ecc_aps_ram__ecc_csr__108cc000__ecc_registerBlock__SEG_L4_ocram_0x0_0x800`	`0x108CC000`	`0x108CC028 - 0x108CC08C`

Size: 32

Offset: 0x28

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_6` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved_6` `RO 0x0`										`RMW_DERRB` `RW 0x0`	`RMW_DERRA` `RW 0x0`	`RMW_SERRB` `RW 0x0`	`RMW_SERRA` `RW 0x0`	`CMPFLGB` `RW 0x0`	`CMPFLGA` `RW 0x0`

MODSTAT Fields


Bit	Name	Description	Access	Reset
31:6	`Reserved_6`	Reserved bitfield added by Magillem	`RO`	`0x0`
5	`RMW_DERRB`	This bit indicates that a RMW access due to a subword access generated a DERR	`RW`	`0x0`
4	`RMW_DERRA`	This bit indicates that a RMW access due to a subword access generated a DERR	`RW`	`0x0`
3	`RMW_SERRB`	This bit indicates that a RMW access due to a subword access generated a SERR	`RW`	`0x0`
2	`RMW_SERRA`	This bit indicates that a RMW access due to a subword access generated a SERR	`RW`	`0x0`
1	`CMPFLGB`	Port B compare status flag	`RW`	`0x0`
0	`CMPFLGA`	Port A compare status flag	`RW`	`0x0`