HRS30
HRS30 - Host Capability Register\n
This register states whether configurable options are available or are not available in the SD/eMMC Host Controller configuration. This register gives such information about features not been covered by the standard capability registers (SRS16-SRS18).
| Module Instance | Base Address | Register Address |
|---|---|---|
i_sdmmc__sdmmc_apb_slv__10808000____HRS____SEG_L4_MP_sdmmc_s_0x0_0x1000
|
0x10808000
|
0x10808078
|
Size: 32
Offset: 0x78
Access: RO
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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HRS30 Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 31:2 |
Reserved_2
|
Reserved bitfield added by Magillem |
RO
|
0x0
|
| 1 |
HS400ESSUP
|
High Speed 400 Enhance Strobe supported\n
This field informs whether HS400 Enhance Strobe mode is supported (1) or is not supported (0).
|
RO
|
0x1
|
| 0 |
CQSUP
|
Command Queuing supported\n
This field informs whether Command Queuing is supported (1) or is not supported (0).
|
RO
|
0x1
|