HRS10
HRS10 - Host Controller SDCLK start point adjustment
| Module Instance | Base Address | Register Address |
|---|---|---|
i_sdmmc__sdmmc_apb_slv__10808000____HRS____SEG_L4_MP_sdmmc_s_0x0_0x1000
|
0x10808000
|
0x10808028
|
Size: 32
Offset: 0x28
Access: RO
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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HRS10 Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 31:23 |
Reserved_2
|
Reserved bitfield added by Magillem |
RO
|
0x0
|
| 22 |
Reserved
|
Reserved |
RW
|
0x0
|
| 21:20 |
Reserved_1
|
Reserved bitfield added by Magillem |
RO
|
0x0
|
| 19:16 |
HCSDCLKADJ
|
HCSDCLKADJ\n
This field allows to adjust flow control mechanism which disables SDCLK. With value 0, the clock (dfi_webar/dfi_webar_high) will be disabled right after end bit of the data block. Increasing this value will cause that clock signal is to be disabled earlier with SDCLK period step.
|
RW
|
0x0
|
| 15:0 |
Reserved_0
|
Reserved bitfield added by Magillem |
RO
|
0x0
|