HRS07 

         HRS07 - IO Delay Information Register
Module Instance Base Address Register Address
i_sdmmc__sdmmc_apb_slv__10808000____HRS____SEG_L4_MP_sdmmc_s_0x0_0x1000 0x10808000 0x1080801C

Size: 32

Offset: 0x1C

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_2

RO 0x0

RW_COMPENSATE

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_1

RO 0x0

IDELAY_VAL

RW 0x0

HRS07 Fields

Bit Name Description Access Reset
31:21 Reserved_2 
Reserved bitfield added by Magillem
 RO 0x0
20:16 RW_COMPENSATE 
              RW_COMPENSATE - Read Wait Compensate value \n
              According to delays between PAD and dfi_rddata, dfi_wrdata and PAD and to Read Wait timing requirements,
              the signal dat[2] should be set to 0 earlier than controller read the end bit of read data.
              Designer should update this register with delay of data path count in sdmclk clock cycles.
              If the value is greater than 10 and value of field SDCLK Frequency Select (concatenation of SRS11.SDCFSH, SRS11.SDCFSL)
              is equal 0, then io_mask_start parameter in PHY register phy_dq_timing_reg should be set with value equal (RW_COMPENSATE-10)*2.
RW 0x0
15:5 Reserved_1 
Reserved bitfield added by Magillem
 RO 0x0
4:0 IDELAY_VAL 
              IDELAY_VAL - Input delay value for IO. \n
              Designer should update this register with delay value of IO with appriopriate input delay. \n
              Delay is count in half of period of sdmclk. If sdmclk is working at 200MHz frequency, \n
              then 1 is 2,5 ns. \n
              This value will be used to compensate delay of DAT line when controller is reading Card Interrupt. \n
RW 0x0