HRS02 

         HRS02 - Bus Setting Register
Module Instance Base Address Register Address
i_sdmmc__sdmmc_apb_slv__10808000____HRS____SEG_L4_MP_sdmmc_s_0x0_0x1000 0x10808000 0x10808008

Size: 32

Offset: 0x8

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_2

RO 0x0

OTN

RW 0x3

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_1

RO 0x0

PBL

RW 0x0

HRS02 Fields

Bit Name Description Access Reset
31:18 Reserved_2 
Reserved bitfield added by Magillem
 RO 0x0
17:16 OTN 
              OTN - Number of Outstanding Transfers\n
              Specifies number of outstanding transfers on DMA (Master) interface. The number of outstadings is (OTN + 1), where OTN can be defined in range 0 to 3.\n
              This register is set to 3 after reset (i.e. 4 outstanding transfers).
RW 0x3
15:4 Reserved_1 
Reserved bitfield added by Magillem
 RO 0x0
3:0 PBL 
              PBL - Programmable Burst Length\n
              This field defines a maximum number of beats in DMA burst. The value can be changed when no active transfer.\n
              This register is 0 after reset.\n
              [list] [*] 0001b - 1 beat in burst [*] 0010b - 2 beats in burst [*] 0011b - 4 beats in burst [*] 0100b - 8 bits in burst [*] other - 16 beats in burst [/list]
RW 0x0