HRS00 

         HRS00 - General Information Register
Module Instance Base Address Register Address
i_sdmmc__sdmmc_apb_slv__10808000____HRS____SEG_L4_MP_sdmmc_s_0x0_0x1000 0x10808000 0x10808000

Size: 32

Offset: 0x

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_2

RO 0x0

SAV

RO 0x1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved_1

RO 0x0

SWR

RW 0x0

HRS00 Fields

Bit Name Description Access Reset
31:24 Reserved_2 
Reserved bitfield added by Magillem
 RO 0x0
23:16 SAV 
              SAV - Slot Available\n
              Field informs that the Host Controller supports one slot.
RO 0x1
15:1 Reserved_1 
Reserved bitfield added by Magillem
 RO 0x0
0 SWR 
              SWR - Software Reset\n

              When set to 1, the entire core is reset. After reset operation complete, SWR bit is automatically cleared. It takes some time to complete the requested reset operation, so the software should always poll SWR bit status, and continue the other operations only when SWR is cleared to 0.\n

              There is no difference between SWR and SRS11.SRFA software resets. Both resets the same flip-flops.
RW 0x0