GPIO_SWPORTA_DR 

         Name: Port A data register
Size: 1-32 bits
Address Offset: 0x00
Read/Write Access: Read/Write
Module Instance Base Address Register Address
i_gpio_1__gpio_csr__10c03300__DW_apb_gpio_addr_block__SEG_L4_SP_gpio1_0x0_0x100 0x10C03300 0x10C03300

Size: 32

Offset: 0x

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_1

RO 0x0

GPIO_SWPORTA_DR

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GPIO_SWPORTA_DR

RW 0x0

GPIO_SWPORTA_DR Fields

Bit Name Description Access Reset
31:24 Reserved_1 
Reserved bitfield added by Magillem
 RO 0x0
23:0 GPIO_SWPORTA_DR 
Values written to this register are output on the I/O signals
for Port A if the corresponding data direction bits for Port A
are set to Output mode and the corresponding control bit for
Port A is set to Software mode. The value read back is equal
to the last value written to this register.
 RW 0x0