GPIO_PORTA_EOI

         Name: Port A clear interrupt register
Size: 1-32 bits
Address Offset: 0x4c
Read/Write Access: Write


Module Instance	Base Address	Register Address
`i_gpio_1__gpio_csr__10c03300__DW_apb_gpio_addr_block__SEG_L4_SP_gpio1_0x0_0x100`	`0x10C03300`	`0x10C0334C`

Size: 32

Offset: 0x4C

Access: WO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_1` `WO 0x0`								`GPIO_PORTA_EOI` `WO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`GPIO_PORTA_EOI` `WO 0x0`

GPIO_PORTA_EOI Fields

Bit Name Description Access Reset

31:24

Reserved_1

Reserved bitfield added by Magillem

WO

0x0

23:0

GPIO_PORTA_EOI

Controls the clearing of edge type interrupts from Port A.
When a 1 is written into a corresponding bit of this register,
the interrupt is cleared. All interrupts are cleared when
Port A is not configured for interrupts.
0  No interrupt clear (default)
1  Clear interrupt

Value	Description
0x0	No interrupt clear
0x1	Clear Interrupt

WO

0x0