GPIO_INTMASK

         Name: Interrupt mask register
Size: 1-32 bits
Address Offset: 0x34
Read/Write Access: Read/Write


Module Instance	Base Address	Register Address
`i_gpio_1__gpio_csr__10c03300__DW_apb_gpio_addr_block__SEG_L4_SP_gpio1_0x0_0x100`	`0x10C03300`	`0x10C03334`

Size: 32

Offset: 0x34

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_1` `RO 0x0`								`GPIO_INTMASK` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`GPIO_INTMASK` `RW 0x0`

GPIO_INTMASK Fields

Bit Name Description Access Reset

31:24

Reserved_1

Reserved bitfield added by Magillem

RO

0x0

23:0

GPIO_INTMASK

Controls whether an interrupt on Port A can create an
interrupt for the interrupt controller by not masking it. By
default, all interrupts bits are unmasked. Whenever a 1 is
written to a bit in this register, it masks the interrupt
generation capability for this signal; otherwise interrupts are
allowed through. The unmasked status can be read as well as
the resultant status after masking.
0  Interrupt bits are unmasked (default)
1  Mask interrupt

Value	Description
0x0	Interrupt bits are unmasked
0x1	Mask interrupt

RW

0x0