XAIUUEDR 

         Unit Uncorrectable Error Detect Register
Module Instance Base Address Register Address
i_ccu__DSU__1c000000__GIC_M 0x1C002000 0x1C002100

Size: 32

Offset: 0x100

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Rsvd1

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Rsvd1

RO 0x0

TimeoutErrDetEn

RW 0x0

DecErrDetEn

RW 0x0

MemErrDetEn

RW 0x0

TransErrDetEn

RW 0x0

ProtErrDetEn

RW 0x0

XAIUUEDR Fields

Bit Name Description Access Reset
31:5 Rsvd1 
Reserved
 RO 0x0
4 TimeoutErrDetEn 
Timeout protection error detection enable: When set, timeout errors will be detected.
 RW 0x0
3 DecErrDetEn 
Decode Error Enable. When set, this bit enables detection of address map uncorrectable error
 RW 0x0
2 MemErrDetEn 
Memory protection error detection enable: When set,errors will be detected from any RAM memory arrays.
 RW 0x0
1 TransErrDetEn 
Concerto Transport error detect enable: When set, errors will be detected from the Concerto Transport.
 RW 0x0
0 ProtErrDetEn 
AXI downstream protocol error detect enable: When set, errors will be detected from the downstream AXI interface.
 RW 0x0