GICT_ERR8FR

         GICT_ERR8FR


Module Instance	Base Address	Register Address
`i_aps_gic__gic_axi4_slave__1d000000__GICT`	`0x1D020000`	`0x1D020200`

Size: 64

Offset: 0x200

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
`RESERVED0` `RO 0x0`
47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
`RESERVED0` `RO 0x0`
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RESERVED0` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RP` `RO 0x0`	`CEC` `RO 0x0`			`CFI` `RO 0x0`		`UE` `RO 0x0`		`FI` `RO 0x0`		`UI` `RO 0x0`		`DE` `RO 0x0`		`ED` `RO 0x0`

GICT_ERR8FR Fields


Bit	Name	Description	Access	Reset
63:16	`RESERVED0`	RESERVED0	`RO`	`0x0`
15	`RP`	RP	`RO`	`0x0`
14:12	`CEC`	CEC	`RO`	`0x0`
11:10	`CFI`	CFI	`RO`	`0x0`
9:8	`UE`	UE	`RO`	`0x0`
7:6	`FI`	FI	`RO`	`0x0`
5:4	`UI`	UI	`RO`	`0x0`
3:2	`DE`	DE	`RO`	`0x0`
1:0	`ED`	ED	`RO`	`0x0`