GICT_ERR4STATUS 

         GICT_ERR4STATUS
Module Instance Base Address Register Address
i_aps_gic__gic_axi4_slave__1d000000__GICT 0x1D020000 0x1D020110

Size: 64

Offset: 0x110

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

RESERVED2

RW 0x0

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RESERVED2

RW 0x0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

AV

RW 0x0

V

RW 0x0

UE

RW 0x0

ER

RW 0x0

OF

RW 0x0

MV

RW 0x0

CE

RW 0x0

RESERVED1

RW 0x0

UET

RW 0x0

RESERVED0

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IERR

RW 0x0

SERR

RW 0x0

GICT_ERR4STATUS Fields

Bit Name Description Access Reset
63:32 RESERVED2 
RESERVED2
 RW 0x0
31 AV 
AV
 RW 0x0
30 V 
V
 RW 0x0
29 UE 
UE
 RW 0x0
28 ER 
ER
 RW 0x0
27 OF 
OF
 RW 0x0
26 MV 
MV
 RW 0x0
25:24 CE 
CE
 RW 0x0
23:22 RESERVED1 
RESERVED1
 RW 0x0
21:20 UET 
UET
 RW 0x0
19:16 RESERVED0 
RESERVED0
 RW 0x0
15:8 IERR 
IERR
 RW 0x0
7:0 SERR 
SERR
 RW 0x0