GICP_IRQCR

         GICP_IRQCR


Module Instance	Base Address	Register Address
`i_aps_gic__gic_axi4_slave__1d000000__GICP`	`0x1D030000`	`0x1D030E50`

Size: 32

Offset: 0xE50

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RESERVED0` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RESERVED0` `RW 0x0`						`SPIID` `RW 0x0`

GICP_IRQCR Fields


Bit	Name	Description	Access	Reset
31:10	`RESERVED0`	RESERVED0	`RW`	`0x0`
9:0	`SPIID`	SPIID	`RW`	`0x0`