GICP_CNTENCLR0

         GICP_CNTENCLR0


Module Instance	Base Address	Register Address
`i_aps_gic__gic_axi4_slave__1d000000__GICP`	`0x1D030000`	`0x1D030C20`

Size: 64

Offset: 0xC20

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
`RESERVED0` `RW 0x0`
47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
`RESERVED0` `RW 0x0`
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RESERVED0` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RESERVED0` `RW 0x0`											`CNTEN4` `RW 0x0`	`CNTEN3` `RW 0x0`	`CNTEN2` `RW 0x0`	`CNTEN1` `RW 0x0`	`CNTEN0` `RW 0x0`

GICP_CNTENCLR0 Fields


Bit	Name	Description	Access	Reset
63:5	`RESERVED0`	RESERVED0	`RW`	`0x0`
4	`CNTEN4`	CNTEN4	`RW`	`0x0`
3	`CNTEN3`	CNTEN3	`RW`	`0x0`
2	`CNTEN2`	CNTEN2	`RW`	`0x0`
1	`CNTEN1`	CNTEN1	`RW`	`0x0`
0	`CNTEN0`	CNTEN0	`RW`	`0x0`