GICP_CFGR

         GICP_CFGR


Module Instance	Base Address	Register Address
`i_aps_gic__gic_axi4_slave__1d000000__GICP`	`0x1D030000`	`0x1D030E00`

Size: 32

Offset: 0xE00

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RESERVED2` `RO 0x0`									`CAPTURE` `RO 0x1`	`RESERVED1` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RESERVED1` `RO 0x0`		`SIZE` `RO 0x1F`						`RESERVED0` `RO 0x0`		`NCTR` `RO 0x4`

GICP_CFGR Fields


Bit	Name	Description	Access	Reset
31:23	`RESERVED2`	RESERVED2	`RO`	`0x0`
22	`CAPTURE`	CAPTURE	`RO`	`0x1`
21:14	`RESERVED1`	RESERVED1	`RO`	`0x0`
13:8	`SIZE`	SIZE	`RO`	`0x1F`
7:6	`RESERVED0`	RESERVED0	`RO`	`0x0`
5:0	`NCTR`	NCTR	`RO`	`0x4`