GICD_IERRR7

         GICD_IERRR7
      
Module Instance Base Address Register Address
i_aps_gic__gic_axi4_slave__1d000000__GICD 0x1D000000 0x1D00E11C

Size: 32

Offset: 0xE11C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

status31

RW 0x0

status30

RW 0x0

status29

RW 0x0

status28

RW 0x0

status27

RW 0x0

status26

RW 0x0

status25

RW 0x0

status24

RW 0x0

status23

RW 0x0

status22

RW 0x0

status21

RW 0x0

status20

RW 0x0

status19

RW 0x0

status18

RW 0x0

status17

RW 0x0

status16

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

status15

RW 0x0

status14

RW 0x0

status13

RW 0x0

status12

RW 0x0

status11

RW 0x0

status10

RW 0x0

status9

RW 0x0

status8

RW 0x0

status7

RW 0x0

status6

RW 0x0

status5

RW 0x0

status4

RW 0x0

status3

RW 0x0

status2

RW 0x0

status1

RW 0x0

status0

RW 0x0

GICD_IERRR7 Fields

Bit Name Description Access Reset
31 status31
status31
RW 0x0
30 status30
status30
RW 0x0
29 status29
status29
RW 0x0
28 status28
status28
RW 0x0
27 status27
status27
RW 0x0
26 status26
status26
RW 0x0
25 status25
status25
RW 0x0
24 status24
status24
RW 0x0
23 status23
status23
RW 0x0
22 status22
status22
RW 0x0
21 status21
status21
RW 0x0
20 status20
status20
RW 0x0
19 status19
status19
RW 0x0
18 status18
status18
RW 0x0
17 status17
status17
RW 0x0
16 status16
status16
RW 0x0
15 status15
status15
RW 0x0
14 status14
status14
RW 0x0
13 status13
status13
RW 0x0
12 status12
status12
RW 0x0
11 status11
status11
RW 0x0
10 status10
status10
RW 0x0
9 status9
status9
RW 0x0
8 status8
status8
RW 0x0
7 status7
status7
RW 0x0
6 status6
status6
RW 0x0
5 status5
status5
RW 0x0
4 status4
status4
RW 0x0
3 status3
status3
RW 0x0
2 status2
status2
RW 0x0
1 status1
status1
RW 0x0
0 status0
status0
RW 0x0