GICD_FCTLR

         GICD_FCTLR


Module Instance	Base Address	Register Address
`i_aps_gic__gic_axi4_slave__1d000000__GICD`	`0x1D000000`	`0x1D000020`

Size: 32

Offset: 0x20

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RESERVED4` `RW 0x0`					`POS` `RW 0x0`	`QDENY` `RW 0x0`	`RESERVED3` `RW 0x0`			`DCC` `RW 0x0`	`RESERVED2` `RW 0x0`			`NSACR` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RESERVED1` `RW 0x0`			`CGO` `RW 0x0`									`RESERVED0` `RW 0x0`			`SIP` `RW 0x0`

GICD_FCTLR Fields


Bit	Name	Description	Access	Reset
31:27	`RESERVED4`	RESERVED4	`RW`	`0x0`
26	`POS`	POS	`RW`	`0x0`
25	`QDENY`	QDENY	`RW`	`0x0`
24:22	`RESERVED3`	RESERVED3	`RW`	`0x0`
21	`DCC`	DCC	`RW`	`0x0`
20:18	`RESERVED2`	RESERVED2	`RW`	`0x0`
17:16	`NSACR`	NSACR	`RW`	`0x0`
15:13	`RESERVED1`	RESERVED1	`RW`	`0x0`
12:4	`CGO`	CGO	`RW`	`0x0`
3:1	`RESERVED0`	RESERVED0	`RW`	`0x0`
0	`SIP`	SIP	`RW`	`0x0`