GICDA_ISPENDR3

         GICDA_ISPENDR3


Module Instance	Base Address	Register Address
`i_aps_gic__gic_axi4_slave__1d000000__GICDA`	`0x1D0E0000`	`0x1D0E020C`

Size: 32

Offset: 0x20C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`set_pending_bit31` `RW 0x0`	`set_pending_bit30` `RW 0x0`	`set_pending_bit29` `RW 0x0`	`set_pending_bit28` `RW 0x0`	`set_pending_bit27` `RW 0x0`	`set_pending_bit26` `RW 0x0`	`set_pending_bit25` `RW 0x0`	`set_pending_bit24` `RW 0x0`	`set_pending_bit23` `RW 0x0`	`set_pending_bit22` `RW 0x0`	`set_pending_bit21` `RW 0x0`	`set_pending_bit20` `RW 0x0`	`set_pending_bit19` `RW 0x0`	`set_pending_bit18` `RW 0x0`	`set_pending_bit17` `RW 0x0`	`set_pending_bit16` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`set_pending_bit15` `RW 0x0`	`set_pending_bit14` `RW 0x0`	`set_pending_bit13` `RW 0x0`	`set_pending_bit12` `RW 0x0`	`set_pending_bit11` `RW 0x0`	`set_pending_bit10` `RW 0x0`	`set_pending_bit9` `RW 0x0`	`set_pending_bit8` `RW 0x0`	`set_pending_bit7` `RW 0x0`	`set_pending_bit6` `RW 0x0`	`set_pending_bit5` `RW 0x0`	`set_pending_bit4` `RW 0x0`	`set_pending_bit3` `RW 0x0`	`set_pending_bit2` `RW 0x0`	`set_pending_bit1` `RW 0x0`	`set_pending_bit0` `RW 0x0`

GICDA_ISPENDR3 Fields


Bit	Name	Description	Access	Reset
31	`set_pending_bit31`	set_pending_bit31	`RW`	`0x0`
30	`set_pending_bit30`	set_pending_bit30	`RW`	`0x0`
29	`set_pending_bit29`	set_pending_bit29	`RW`	`0x0`
28	`set_pending_bit28`	set_pending_bit28	`RW`	`0x0`
27	`set_pending_bit27`	set_pending_bit27	`RW`	`0x0`
26	`set_pending_bit26`	set_pending_bit26	`RW`	`0x0`
25	`set_pending_bit25`	set_pending_bit25	`RW`	`0x0`
24	`set_pending_bit24`	set_pending_bit24	`RW`	`0x0`
23	`set_pending_bit23`	set_pending_bit23	`RW`	`0x0`
22	`set_pending_bit22`	set_pending_bit22	`RW`	`0x0`
21	`set_pending_bit21`	set_pending_bit21	`RW`	`0x0`
20	`set_pending_bit20`	set_pending_bit20	`RW`	`0x0`
19	`set_pending_bit19`	set_pending_bit19	`RW`	`0x0`
18	`set_pending_bit18`	set_pending_bit18	`RW`	`0x0`
17	`set_pending_bit17`	set_pending_bit17	`RW`	`0x0`
16	`set_pending_bit16`	set_pending_bit16	`RW`	`0x0`
15	`set_pending_bit15`	set_pending_bit15	`RW`	`0x0`
14	`set_pending_bit14`	set_pending_bit14	`RW`	`0x0`
13	`set_pending_bit13`	set_pending_bit13	`RW`	`0x0`
12	`set_pending_bit12`	set_pending_bit12	`RW`	`0x0`
11	`set_pending_bit11`	set_pending_bit11	`RW`	`0x0`
10	`set_pending_bit10`	set_pending_bit10	`RW`	`0x0`
9	`set_pending_bit9`	set_pending_bit9	`RW`	`0x0`
8	`set_pending_bit8`	set_pending_bit8	`RW`	`0x0`
7	`set_pending_bit7`	set_pending_bit7	`RW`	`0x0`
6	`set_pending_bit6`	set_pending_bit6	`RW`	`0x0`
5	`set_pending_bit5`	set_pending_bit5	`RW`	`0x0`
4	`set_pending_bit4`	set_pending_bit4	`RW`	`0x0`
3	`set_pending_bit3`	set_pending_bit3	`RW`	`0x0`
2	`set_pending_bit2`	set_pending_bit2	`RW`	`0x0`
1	`set_pending_bit1`	set_pending_bit1	`RW`	`0x0`
0	`set_pending_bit0`	set_pending_bit0	`RW`	`0x0`