GICDA_ICENABLER7

         GICDA_ICENABLER7


Module Instance	Base Address	Register Address
`i_aps_gic__gic_axi4_slave__1d000000__GICDA`	`0x1D0E0000`	`0x1D0E019C`

Size: 32

Offset: 0x19C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`clear_enable_bit31` `RW 0x0`	`clear_enable_bit30` `RW 0x0`	`clear_enable_bit29` `RW 0x0`	`clear_enable_bit28` `RW 0x0`	`clear_enable_bit27` `RW 0x0`	`clear_enable_bit26` `RW 0x0`	`clear_enable_bit25` `RW 0x0`	`clear_enable_bit24` `RW 0x0`	`clear_enable_bit23` `RW 0x0`	`clear_enable_bit22` `RW 0x0`	`clear_enable_bit21` `RW 0x0`	`clear_enable_bit20` `RW 0x0`	`clear_enable_bit19` `RW 0x0`	`clear_enable_bit18` `RW 0x0`	`clear_enable_bit17` `RW 0x0`	`clear_enable_bit16` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`clear_enable_bit15` `RW 0x0`	`clear_enable_bit14` `RW 0x0`	`clear_enable_bit13` `RW 0x0`	`clear_enable_bit12` `RW 0x0`	`clear_enable_bit11` `RW 0x0`	`clear_enable_bit10` `RW 0x0`	`clear_enable_bit9` `RW 0x0`	`clear_enable_bit8` `RW 0x0`	`clear_enable_bit7` `RW 0x0`	`clear_enable_bit6` `RW 0x0`	`clear_enable_bit5` `RW 0x0`	`clear_enable_bit4` `RW 0x0`	`clear_enable_bit3` `RW 0x0`	`clear_enable_bit2` `RW 0x0`	`clear_enable_bit1` `RW 0x0`	`clear_enable_bit0` `RW 0x0`

GICDA_ICENABLER7 Fields


Bit	Name	Description	Access	Reset
31	`clear_enable_bit31`	clear_enable_bit31	`RW`	`0x0`
30	`clear_enable_bit30`	clear_enable_bit30	`RW`	`0x0`
29	`clear_enable_bit29`	clear_enable_bit29	`RW`	`0x0`
28	`clear_enable_bit28`	clear_enable_bit28	`RW`	`0x0`
27	`clear_enable_bit27`	clear_enable_bit27	`RW`	`0x0`
26	`clear_enable_bit26`	clear_enable_bit26	`RW`	`0x0`
25	`clear_enable_bit25`	clear_enable_bit25	`RW`	`0x0`
24	`clear_enable_bit24`	clear_enable_bit24	`RW`	`0x0`
23	`clear_enable_bit23`	clear_enable_bit23	`RW`	`0x0`
22	`clear_enable_bit22`	clear_enable_bit22	`RW`	`0x0`
21	`clear_enable_bit21`	clear_enable_bit21	`RW`	`0x0`
20	`clear_enable_bit20`	clear_enable_bit20	`RW`	`0x0`
19	`clear_enable_bit19`	clear_enable_bit19	`RW`	`0x0`
18	`clear_enable_bit18`	clear_enable_bit18	`RW`	`0x0`
17	`clear_enable_bit17`	clear_enable_bit17	`RW`	`0x0`
16	`clear_enable_bit16`	clear_enable_bit16	`RW`	`0x0`
15	`clear_enable_bit15`	clear_enable_bit15	`RW`	`0x0`
14	`clear_enable_bit14`	clear_enable_bit14	`RW`	`0x0`
13	`clear_enable_bit13`	clear_enable_bit13	`RW`	`0x0`
12	`clear_enable_bit12`	clear_enable_bit12	`RW`	`0x0`
11	`clear_enable_bit11`	clear_enable_bit11	`RW`	`0x0`
10	`clear_enable_bit10`	clear_enable_bit10	`RW`	`0x0`
9	`clear_enable_bit9`	clear_enable_bit9	`RW`	`0x0`
8	`clear_enable_bit8`	clear_enable_bit8	`RW`	`0x0`
7	`clear_enable_bit7`	clear_enable_bit7	`RW`	`0x0`
6	`clear_enable_bit6`	clear_enable_bit6	`RW`	`0x0`
5	`clear_enable_bit5`	clear_enable_bit5	`RW`	`0x0`
4	`clear_enable_bit4`	clear_enable_bit4	`RW`	`0x0`
3	`clear_enable_bit3`	clear_enable_bit3	`RW`	`0x0`
2	`clear_enable_bit2`	clear_enable_bit2	`RW`	`0x0`
1	`clear_enable_bit1`	clear_enable_bit1	`RW`	`0x0`
0	`clear_enable_bit0`	clear_enable_bit0	`RW`	`0x0`