GICDA_CTLR

         GICDA_CTLR


Module Instance	Base Address	Register Address
`i_aps_gic__gic_axi4_slave__1d000000__GICDA`	`0x1D0E0000`	`0x1D0E0000`

Size: 32

Offset: 0x

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RWP` `RO 0x0`	`RESERVED1` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RESERVED1` `RW 0x0`								`E1NWF` `RW 0x0`	`DS` `RO 0x0`	`ARE_NS` `RW 0x1`	`ARE_S` `RW 0x1`	`RESERVED0` `RW 0x0`	`EnableGrp1_s` `RW 0x0`	`EnableGrp1_ns` `RW 0x0`	`EnableGrp0` `RW 0x0`

GICDA_CTLR Fields


Bit	Name	Description	Access	Reset
31	`RWP`	RWP	`RO`	`0x0`
30:8	`RESERVED1`	RESERVED1	`RW`	`0x0`
7	`E1NWF`	E1NWF	`RW`	`0x0`
6	`DS`	DS	`RO`	`0x0`
5	`ARE_NS`	ARE_NS	`RW`	`0x1`
4	`ARE_S`	ARE_S	`RW`	`0x1`
3	`RESERVED0`	RESERVED0	`RW`	`0x0`
2	`EnableGrp1_s`	EnableGrp1_s	`RW`	`0x0`
1	`EnableGrp1_ns`	EnableGrp1_ns	`RW`	`0x0`
0	`EnableGrp0`	EnableGrp0	`RW`	`0x0`