LU3LFPSRXTIM

         U3 LFPS RX TIMER REGS REGISTER
      
Module Instance Base Address Register Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_link__SEG_L4_AHB_USB1_0x0_0x100000 0x1100D000 0x1100D010

Size: 32

Offset: 0x10

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

gen2_u3_lfps_exit_rx_clk

RW 0x9C

gen2_u3_exit_rsp_rx_clk

RW 0x6

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

gen1_u3_lfps_exit_rx_clk

RW 0x7D

gen1_u3_exit_rsp_rx_clk

RW 0x5

LU3LFPSRXTIM Fields

Bit Name Description Access Reset
31:24 gen2_u3_lfps_exit_rx_clk RW 0x9C
23:16 gen2_u3_exit_rsp_rx_clk RW 0x6
15:8 gen1_u3_lfps_exit_rx_clk RW 0x7D
7:0 gen1_u3_exit_rsp_rx_clk RW 0x5