LU2LFPSTXTIM

         U2 LFPS TX TIMER REG REGISTER


Module Instance	Base Address	Register Address
`i_usb31_0__ahb_slave__11000000__DWC_usb31_block_link__SEG_L4_AHB_USB1_0x0_0x100000`	`0x1100D000`	`0x1100D00C`

Size: 32

Offset: 0xC

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`reserved_1` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`reserved_1` `RO 0x0`		`u2_exit_rsp_tx_us` `RW 0x52`

LU2LFPSTXTIM Fields

Bit Name Description Access Reset

31:14

Bit	Name	Description	Access	Reset
31:14	`reserved_1`	Reserved	`RO`	`0x0`
13:0	`u2_exit_rsp_tx_us`	U2_EXIT_RESP_TX_US - Remotely initiated Ux exit: Local link will transmit response this long before initiating transition to Recovery. - When P3 in U2 is enabled, software needs to program this according to suspend_clk - This field is encoded as the number of us count for the LFPS. -- 1 : 1us -- 2 : 2us -- 3 : 3us, and so on	`RW`	`0x52`

reserved_1

Reserved

RO

0x0

13:0

u2_exit_rsp_tx_us

U2_EXIT_RESP_TX_US
   - Remotely initiated Ux exit: Local link will transmit response this long before initiating transition to Recovery.
   - When P3 in U2 is enabled, software needs to program this according to suspend_clk
   - This field is encoded as the number of us count for the LFPS.
   -- 1 : 1us
   -- 2 : 2us
   -- 3 : 3us, and so on

RW

0x52