LU1LFPSTXTIM 

         U1 LFPS TX TIMER REGISTER
Module Instance Base Address Register Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_link__SEG_L4_AHB_USB1_0x0_0x100000 0x1100D000 0x1100D004

Size: 32

Offset: 0x4

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved_2

RO 0x0

gen2_u1_exit_resp_tx_clk

RW 0x94

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved_1

RO 0x0

gen1_u1_exit_rsp_tx_clk

RW 0x76

LU1LFPSTXTIM Fields

Bit Name Description Access Reset
31:30 reserved_2 
Reserved
 RO 0x0
29:16 gen2_u1_exit_resp_tx_clk 
gen2 U1_EXIT_RESP_TX_CLKS
   - Remotely initiated Ux exit: Local link will transmit response this long before initiating transition to Recovery (t13 - t11)
   - This field is encoded as the Gen2 link_clk (6.4ns) count for the LFPS.
   -- 1: 6.4ns
   -- 2: 12.8ns
   -- 3: 19.2ns, and so on
RW 0x94
15:14 reserved_1 
Reserved
 RO 0x0
13:0 gen1_u1_exit_rsp_tx_clk 
gen1 U1_EXIT_RESP_TX_CLKS
   - Remotely initiated Ux exit: Local link will transmit response this long before initiating transition to Recovery (t13 - t11
   - This field is encoded as the Gen1 link_clk (8ns) count for the LFPS.
   -- 1: 8ns
   -- 2: 16ns
   -- 3: 24ns, and so on
RW 0x76