LSCDTIM1

         SCD TIMER 1 REGISTER


Module Instance	Base Address	Register Address
`i_usb31_0__ahb_slave__11000000__DWC_usb31_block_link__SEG_L4_AHB_USB1_0x0_0x100000`	`0x1100D000`	`0x1100D02C`

Size: 32

Offset: 0x2C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_1` `RO 0x0`								`scd_bit0_rpt_max_clk` `RW 0x47E`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`scd_bit0_rpt_max_clk` `RW 0x47E`				`cd_bit0_rpt_min_clk` `RW 0x1F4`

LSCDTIM1 Fields

Bit Name Description Access Reset

31:24

Bit	Name	Description	Access	Reset
31:24	`Reserved_1`	Reserved_1	`RO`	`0x0`
23:12	`scd_bit0_rpt_max_clk`	SCD_BIT0_REPEAT_MAX_CLKS - max duration of SCD bit 0 tRepeat in term of CLKs, used in SCD detection FSM - This field is encoded as the Gen1 link_clk (8ns) count for the LFPS. -- 1: 8ns -- 2: 16ns -- 3: 24ns, and so on	`RW`	`0x47E`
11:0	`cd_bit0_rpt_min_clk`	CD_BIT0_REPEAT_MIN_CLKS - min duration of SCD bit 0 tRepeat in term of CLKs, used in SCD detection FSM - This field is encoded as the Gen1 link_clk (8ns) count for the LFPS. -- 1 : 8ns -- 2 : 16ns -- 3 : 24ns, and so on	`RW`	`0x1F4`

Reserved_1

Reserved_1

RO

0x0

23:12

scd_bit0_rpt_max_clk

SCD_BIT0_REPEAT_MAX_CLKS
   - max duration of SCD bit 0 tRepeat in term of CLKs, used in SCD detection FSM
   - This field is encoded as the Gen1 link_clk (8ns) count for the LFPS.
   -- 1: 8ns
   -- 2: 16ns
   -- 3: 24ns, and so on

RW

0x47E

11:0

cd_bit0_rpt_min_clk

CD_BIT0_REPEAT_MIN_CLKS
   - min duration of SCD bit 0 tRepeat in term of CLKs, used in SCD detection FSM
   - This field is encoded as the Gen1 link_clk (8ns) count for the LFPS.
   -- 1 : 8ns
   -- 2 : 16ns
   -- 3 : 24ns, and so on

RW

0x1F4