LPTMDPDELAY2

         PTM DATAPATH DELAY REGISTER2
   - This register provide an option to override the default timing parameters used in PTM calculation.


Module Instance	Base Address	Register Address
`i_usb31_0__ahb_slave__11000000__DWC_usb31_block_link__SEG_L4_AHB_USB1_0x0_0x100000`	`0x1100D000`	`0x1100D078`

Size: 32

Offset: 0x78

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_1` `RO 0x0`												`link_rx_delay_gen2` `RW 0xA`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`link_rx_delay_gen2` `RW 0xA`	`link_tx_delay_gen2` `RW 0x5`					`link_rx_delay_gen1` `RW 0xB`					`link_tx_delay_gen1` `RW 0x5`

LPTMDPDELAY2 Fields


Bit	Name	Description	Access	Reset
31:20	`Reserved_1`	Reserved_1	`RO`	`0x0`
19:15	`link_rx_delay_gen2`	link_rx_delay_gen2 RX path delay in unit of 8ns	`RW`	`0xA`
14:10	`link_tx_delay_gen2`	link_tx_delay_gen2 RX path delay in unit of 8ns	`RW`	`0x5`
9:5	`link_rx_delay_gen1`	link_rx_delay_gen1 RX path delay in unit of 8ns	`RW`	`0xB`
4:0	`link_tx_delay_gen1`	link_tx_delay_gen1 TX path delay in unit of 8ns	`RW`	`0x5`