LPTMDPDELAY

         PTM DATAPATH DELAY REGISTER
  
  This register provides an option to override the default timing parameters used in PTM calculation.


Module Instance	Base Address	Register Address
`i_usb31_0__ahb_slave__11000000__DWC_usb31_block_link__SEG_L4_AHB_USB1_0x0_0x100000`	`0x1100D000`	`0x1100D028`

Size: 32

Offset: 0x28

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`rx_path_delay_gen2` `RW 0x0`					`tx_path_delay_gen2` `RW 0x0`					`p3cpmp4_residency` `RW 0x3`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`p3cpmp4_residency` `RW 0x3`						`rx_path_delay` `RW 0x0`					`tx_path_delay` `RW 0x0`

LPTMDPDELAY Fields


Bit	Name	Description	Access	Reset
31:27	`rx_path_delay_gen2`	rx_path_delay_gen2 RX path delay in unit of 8ns	`RW`	`0x0`
26:22	`tx_path_delay_gen2`	tx_path_delay_gen2 TX path delay in unit of 8ns	`RW`	`0x0`
21:10	`p3cpmp4_residency`	Minimum number of suspend_clk periods that the PHY needs to stay in P3.CPM or P4 before exiting P3.CPM or P4.	`RW`	`0x3`
9:5	`rx_path_delay`	rx_path_delay Gen1 RX path delay (including PHY and PCS) in terms of 8ns.	`RW`	`0x0`
4:0	`tx_path_delay`	tx_path_delay Gen1 TX path delay (including PHY and PCS) in terms of 8ns.	`RW`	`0x0`