LLUCTL 

         TX TS1 COUNT REGISTER
   - This register provides an option to increase the number of TS1 sent in Polling.Active or Recovery.Active.
   - The total number of TS1 during Polling.Active or Recovery.Active is based on the following formula: 
  Total TS1 = 20 x 2^(tx_ts1_cnt)
   - This give more opportunity for the remote PHY to achive symbol lock.
Module Instance Base Address Register Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_link__SEG_L4_AHB_USB1_0x0_0x100000 0x1100D000 0x1100D024

Size: 32

Offset: 0x24

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_31

RW 0x0

inverse_sync_header

RW 0x0

support_p4_pg

RW 0x0

support_p4

RW 0x0

delay_tx_gen1_dp

RW 0x0

DisRxDet_LTSSM_Timer_Ovrrd

RW 0x1

force_dpp_truncate

RW 0x0

en_dpp_truncate

RW 0x0

pending_hp_timer_us

RW 0xB

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

en_us_hp_timer

RW 0x1

ring_buf_d_delay

RW 0x0

U2P3CPMok

RW 0x0

en_reset_pipe_after_phy_mux

RW 0x0

force_gen1

RW 0x0

gen2_loopback_entry_mode

RW 0x0

gen1_loopback_entry_mode

RW 0x0

mask_pipe_reset

RW 0x1

delay_ux_after_lpma

RW 0x0

no_ux_exit_p0_trans

RW 0x0

tx_ts1_cnt

RW 0x0

LLUCTL Fields

Bit Name Description Access Reset
31 Reserved_31 
Reserved
 RW 0x0
30 inverse_sync_header 
For Gen2 polarity detection, link uses data block (0011b) sync header for SYNC OS instead of control block (1100b).
  
  Set this bit if the third-party PHY does not correct the sync header of the SYNC OS in case of inverse polarity.
 RW 0x0
29 support_p4_pg 
PHY P4 Power gate mode (PG) is enabled.
  
   Set this bit if PHY support PG mode in P4.  Used only for Synopsys PHY
 RW 0x0
28 support_p4 
Support PHY P3.CPM and P4.
  
   When this bit is set, controller puts PHY into P3.CPM or P4 in certain states.  Used only for Synopsys PHY
 RW 0x0
27:24 delay_tx_gen1_dp 
delay_tx_gen1_dp.
  
  When this field is set to a non-zero value, the link delays the transmission of a large Gen1 DP for 32 pipe_pclk cycles if it detects a header being received at the PIU.
 RW 0x0
23 DisRxDet_LTSSM_Timer_Ovrrd 
DisRxDet_LTSSM_Timer_Ovrrd.
  
   When DisRxDetU3RxDet is asserted in Polling or U1, the timeout expires immediately
 RW 0x1
22 force_dpp_truncate 
force_dpp_truncate.
  
  Truncate Gen1 DPP if there is a pending LGOOD/LBAD and DPP is large. When this bit is set, the logic for detecting recovery due to expiring pending_HP_timer is not used.
 RW 0x0
21 en_dpp_truncate 
en_dpp_truncate.
  
  This bit enables the logic for detecting recovery due to expiring pending_HP_timer and truncates DPP when neccessary to avoid recovery.
 RW 0x0
20:16 pending_hp_timer_us 
pending_hp_timer_us.
  
  Programmable PENDING_HP_TIMER in us. This field is used when LUCTL[15] is set.
 RW 0xB
15 en_us_hp_timer 
en_us_hp_timer.
  
  This bit enables programmable PENDING_HP_TIMER in us
 RW 0x1
14:13 ring_buf_d_delay 
ring_buf_d_delay.
  
  This programs the counter for data valid signal in source ring buffer
 RW 0x0
12 U2P3CPMok 
P3CPM OK for U2/SSInactive (U2P3CPMok) 
   - 0: During link state U2/ESS.Inactive, put PHY in P2 (Default)
   - 1: During link state U2/ESS.Inactive, put PHY in P3CPM.
  Note: For a port, if both GUSB3PIPECTL[29]=1 and LLUCTL[12]=1, LLUCTL[12]=1 takes priority.
 RW 0x0
11 en_reset_pipe_after_phy_mux 
en_reset_pipe_after_phy_mux.
  
  controller issues 3.1 PHY reset after DisRxDetU3RxDet is de-asserted
 RW 0x0
10 force_gen1 
Force Gen1
 RW 0x0
9 gen2_loopback_entry_mode 
Gen2 loopback entry mode.
  
  If this bit is set, the controller will enter loopback in Gen2 after successfully detecting remote termination.
 RW 0x0
8 gen1_loopback_entry_mode 
Gen1 loopback entry mode.
  
  If this bit is set, the controller will enter loopback in Gen1 after successfully detecting remote termination.
 RW 0x0
7 mask_pipe_reset 
Mask pipe reset.
  
  If this bit is set, controller will block pipe_reset_n from going to PHY when DisRxDetU3RxDet=1
 RW 0x1
6 delay_ux_after_lpma 
delay_ux_after_lpma. 
   - If this bit is set to 0, after sending LPMA, Link LTSSM delays 10 link_clk cycles before entering Ux.
   - If this bit is set to 1, after sending LPMA, Link LTSSM delays 20 link_clk cycles before entering Ux.
 RW 0x0
5 no_ux_exit_p0_trans 
no_ux_exit_p0_trans. 
   - If this bit is 0, Link LTSSM detects Ux_exit LFPS during P0 transition. 
   - If this bit is set to 1, the Link LTSSM does not detect Ux_exit LFPS when P0 transition is happening.
 RW 0x0
4:0 tx_ts1_cnt 
Additional TX_TS1_count
 RW 0x0