LLPBMTIM2

         LPBM TIMER2 REGISTER


Module Instance	Base Address	Register Address
`i_usb31_0__ahb_slave__11000000__DWC_usb31_block_link__SEG_L4_AHB_USB1_0x0_0x100000`	`0x1100D000`	`0x1100D040`

Size: 32

Offset: 0x40

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved_1` `RO 0x0`														`lfps_lbpm_tpwm_max_clk` `RW 0x136`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`lfps_lbpm_tpwm_max_clk` `RW 0x136`							`lfps_lbpm_tpwm_min_clk` `RW 0xF5`

LLPBMTIM2 Fields

Bit Name Description Access Reset

31:18

Bit	Name	Description	Access	Reset
31:18	`Reserved_1`	Reserved_1	`RO`	`0x0`
17:9	`lfps_lbpm_tpwm_max_clk`	LFPS_LBPM_TPWM_MAX_CLKS - Max value of TPWM, used in LPBM detection FSM - This field is encoded as the Gen1 link_clk (8ns) count. -- 1: 8ns -- 2: 16ns -- 3: 24ns, and so on	`RW`	`0x136`
8:0	`lfps_lbpm_tpwm_min_clk`	LFPS_LBPM_TPWM_MIN_CLKS - Min value of TPWM, used in LPBM detection FSM - This field is encoded as the Gen1 link_clk (8ns) count. -- 1: 8ns -- 2: 16ns -- 3: 24ns, and so on	`RW`	`0xF5`

Reserved_1

Reserved_1

RO

0x0

17:9

lfps_lbpm_tpwm_max_clk

LFPS_LBPM_TPWM_MAX_CLKS
   - Max value of TPWM, used in LPBM detection FSM
   - This field is encoded as the Gen1 link_clk (8ns) count.
   -- 1: 8ns
   -- 2: 16ns
   -- 3: 24ns, and so on

RW

0x136

8:0

lfps_lbpm_tpwm_min_clk

LFPS_LBPM_TPWM_MIN_CLKS
   - Min value of TPWM, used in LPBM detection FSM
   - This field is encoded as the Gen1 link_clk (8ns) count.
   -- 1: 8ns
   -- 2: 16ns
   -- 3: 24ns, and so on

RW

0xF5