LLINKERRINJEN 

         LINK ERROR INJECT ENABLE REGISTER
   - This register is for injecting N number of errors for every M number of packets
Module Instance Base Address Register Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_link__SEG_L4_AHB_USB1_0x0_0x100000 0x1100D000 0x1100D04C

Size: 32

Offset: 0x4C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

disable_inj_err_cnt

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

B2B_err_cnt

RW 0x0

LLINKERRINJEN Fields

Bit Name Description Access Reset
31:16 disable_inj_err_cnt 
Disable injected error count
   - This error specifies the interval of error free between 2 error injection periods.
   - In the case of PIPE data error injection, this field specify the number of microsecond between every bit error injection
 RW 0x0
15:0 B2B_err_cnt 
B2B error count
   - This counter indicates the number of error to be injected consecutively.
   - For instance, the RX CRC5 error type is selected and this counter value is 3, then the next 3 received headers will have invalid CRC5
 RW 0x0