LLINKERRINJ

         LINK ERROR TYPE INJECT REGISTER


Module Instance	Base Address	Register Address
`i_usb31_0__ahb_slave__11000000__DWC_usb31_block_link__SEG_L4_AHB_USB1_0x0_0x100000`	`0x1100D000`	`0x1100D048`

Size: 32

Offset: 0x48

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`pipe_txdata` `RW 0x0`	`TX_insert_defer` `RW 0x0`	`TX_insert_delay` `RW 0x0`	`TX_TS2` `RW 0x0`	`TX_TS1` `RW 0x0`	`TX_TSEQ` `RW 0x0`	`TX_LFR` `RW 0x0`	`TX_delay_credit_rl` `RW 0x0`	`TX_one_srt_frame_sybl` `RW 0x0`	`TX_all_end_frame_sybl` `RW 0x0`	`TX_one_end_frame_sybl` `RW 0x0`	`TX_all_frame_sybl` `RW 0x0`	`TX_one_frame_sybl` `RW 0x0`	`TX_CRC32` `RW 0x0`	`TX_CRC16` `RW 0x0`	`TX_CRC5` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Rx_pipe_rxdata` `RW 0x0`	`RX_insert_defer` `RW 0x0`	`RX_insert_delay` `RW 0x0`	`RX_TS2` `RW 0x0`	`RX_TS1` `RW 0x0`	`RX_TSEQ` `RW 0x0`	`RX_LFR` `RW 0x0`	`RX_all_start_frame_sybl` `RW 0x0`	`RX_one_srt_frame_sybl` `RW 0x0`	`RX_all_end_frame_sybl` `RW 0x0`	`RX_one_end_frame_sybl` `RW 0x0`	`RX_all_frame_sybl` `RW 0x0`	`RX_one_frame_sybl` `RW 0x0`	`RX_CRC32` `RW 0x0`	`RX_CRC16` `RW 0x0`	`RX_CRC5` `RW 0x0`

LLINKERRINJ Fields


Bit	Name	Description	Access	Reset
31	`pipe_txdata`	PIPE TxData - Inject single bit error to TxData. - This includes additional logic to ensure IDLE symbols at the end of recovery aren't corrupted so that link won't enter recovery loop.	`RW`	`0x0`
30	`TX_insert_defer`	TX Insert Deferred Bit	`RW`	`0x0`
29	`TX_insert_delay`	TX Insert Delayed Bit	`RW`	`0x0`
28	`TX_TS2`	TX_TS2 : Corrupt entired TS2	`RW`	`0x0`
27	`TX_TS1`	TX_TS1 : Corrupt entired TS1	`RW`	`0x0`
26	`TX_TSEQ`	TX_TSEQ : Corrupt entired TSEQ	`RW`	`0x0`
25	`TX_LFR`	TX_LFR - Transmitted DPH will have invalid LFR	`RW`	`0x0`
24	`TX_delay_credit_rl`	TX Delay credit release - when this bit is set, link will wait for the amount of microsecond specified in the Error Enable Counter register [15:0]	`RW`	`0x0`
23	`TX_one_srt_frame_sybl`	TX DPP all start framing symbol - all framing symbols of DPP (SDP and EPF) will be corrupted	`RW`	`0x0`
22	`TX_all_end_frame_sybl`	TX DPP all end framing symbol - all framing symbols of DPP (END and EPF) will be corrupted	`RW`	`0x0`
21	`TX_one_end_frame_sybl`	TX DPP one end framing symbol - one framing symbol of DPP (END) will be corrupted	`RW`	`0x0`
20	`TX_all_frame_sybl`	TX TPH/DPH all framing symbol - all framing symbols of TPH/DPH (SHP, DPHP, EPF) will be corrupted	`RW`	`0x0`
19	`TX_one_frame_sybl`	TX TPH/DPH one framing symbol - One framing symbol of TPH/DPH (SHP or DPHP) will be corrupted	`RW`	`0x0`
18	`TX_CRC32`	TX_CRC32 - Transmitted DPP will have invalid CRC32	`RW`	`0x0`
17	`TX_CRC16`	TX_CRC16 - Transmitted header will have invalid CRC16	`RW`	`0x0`
16	`TX_CRC5`	TX_CRC5 - Transmitted header will have CRC error in Link Control Word	`RW`	`0x0`
15	`Rx_pipe_rxdata`	Rx_pipe_rxdata - Inject single bit error to RxData. - This includes additional logic to ensure IDLE symbols at the end of recovery aren't corrupted so that link won't enter recovery loop.	`RW`	`0x0`
14	`RX_insert_defer`	RX_insert_defer	`RW`	`0x0`
13	`RX_insert_delay`	RX_insert_delay	`RW`	`0x0`
12	`RX_TS2`	RX_TS2 - Corrupt entired TS2	`RW`	`0x0`
11	`RX_TS1`	RX_TS1 - Corrupt entired TS1	`RW`	`0x0`
10	`RX_TSEQ`	RX_TSEQ - Corrupt entired TSEQ	`RW`	`0x0`
9	`RX_LFR`	RX_LFR - Received DPH will have invalid LFR	`RW`	`0x0`
8	`RX_all_start_frame_sybl`	DPP all start framing symbol - Before 64-bit received data is forwarded to parser, all framing symbols (SDP or EPF) will be corrupted. - Note: because the entire framing symbol may not be aligned and presented on the 64-bit received data, 1 - 4 framing symbols will be corrupted	`RW`	`0x0`
7	`RX_one_srt_frame_sybl`	DPP one start framing symbol - Before received data is forwarded to parser in RPKT, only one framing symbol (SDP or EPF) will be corrupted	`RW`	`0x0`
6	`RX_all_end_frame_sybl`	DPP all end framing symbol - Before 64-bit received data is forwarded to parser, all framing symbols (END or EPF) will be corrupted. - Note: Because the entire framing symbol may not be aligned and presented on the 64-bit received data, 1 - 4 framing symbols will be corrupted	`RW`	`0x0`
5	`RX_one_end_frame_sybl`	RX DPP one end framing symbol - Before received data is forwarded to parser in RPKT, only one framing symbol (END or EPF) will be corrupted	`RW`	`0x0`
4	`RX_all_frame_sybl`	RX TPH/DPH all framing symbol - Before 64-bit received data is forwarded to parser, all framing symbols (SHP or EPF or DPHP) will be corrupted. - Note: Because the entire framing symbol may not be aligned and presented on the 64-bit received data, 1 - 4 framing symbols will be corrupted	`RW`	`0x0`
3	`RX_one_frame_sybl`	RX TPH/DPH one framing symbol - Before received data is forwarded to parser in RPKT, only one framing symbol (SHP or EPF or DPHP) will be corrupted	`RW`	`0x0`
2	`RX_CRC32`	RX_CRC32 - Received DPP will have invalid CRC32 value	`RW`	`0x0`
1	`RX_CRC16`	RX_CRC16 - Received header will have invalid CRC16 value	`RW`	`0x0`
0	`RX_CRC5`	RX_CRC5 - Received header will have invalid CRC5 value in Link Control Word	`RW`	`0x0`