LLINKDBGCTRL 

         LINK DEBUG CONTROL REGISTER
   - This register is used for link debug purpose.
Module Instance Base Address Register Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_link__SEG_L4_AHB_USB1_0x0_0x100000 0x1100D000 0x1100D058

Size: 32

Offset: 0x58

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

retry_DP

RW 0x0

trigger_end_sts

RO 0x0

trigger_start_sts

RO 0x0

link_state_trigger_descrambled

RW 0x0

link_state_trigger_scrambled

RW 0x0

pipe_txdetectrxlb_trigger

RW 0x0

pipe_rxlecidle_trigger

RW 0x0

pipe_phystatus_trigger

RW 0x0

sub_state_trigger

RW 0x0

link_state_trigger

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

peri_rsc_rxfifo_number

RW 0x0

peri_rsc_txfifo_number

RW 0x0

rxfifo_number

RW 0x0

txfifo_number

RW 0x0

LLINKDBGCTRL Fields

Bit Name Description Access Reset
31 retry_DP 
Link retries full DP instead of DPH in Gen2.  When link needs to resend header due to LBAD or recovery replay, enabling this bit makes link to send full DPH + DPP.  This workaround is for a non-compliance 3.1 device
 RW 0x0
30 trigger_end_sts 
Trigger End Status
 RO 0x0
29 trigger_start_sts 
Trigger Start Status
 RO 0x0
28 link_state_trigger_descrambled 
Link State Trigger Descrambled Debug Control
  
  When set, the controller writes the descrambled received data into the RAM.  The received data is the output of the descrambler.
  
  The link  starts writing debug data based on the following conditions:
   - Link_state and sub_state match the link_state_trigger and sub_state_trigger field, respectively.  After this condition occurs, the link internal debug_byte_count starts incrementing for every link clock, based on the number of bytes to be written to the RAM.  For example, if MDWIDTH=128, the debug_byte_count increments by 16 every link_clk. 
   - Link internal debug_byte_count reaches the start_count_trigger field.
  The link stops writing debug data when the link internal debug_byte_count reaches the stop_count_trigger field.  If stop_count is zero, the link writes out data continuously.
 RW 0x0
27 link_state_trigger_scrambled 
Link State Trigger Scrambled Debug Control
  
  When set, controller writes the PIPE received data into the RAM. The received data is scrambled.
  
  The link  starts writing debug data based on the following conditions:
   - Link_state and sub_state match the link_state_trigger and sub_state_trigger field, respectively. After this condition occurs, the link internal debug_byte_count starts incrementing for every link clock, based on the number of bytes to be written to RAM.  For example, if MDWIDTH=64, the debug_byte_count increments by 8 every link_clk.
   - Link internal debug_byte_count reaches the start_count_trigger field
  The link stops writing debug data when the link internal debug_byte_count reaches the stop_count_trigger field.  If stop_count is zero, the link writes out data continuously.
 RW 0x0
26 pipe_txdetectrxlb_trigger 
PIPE TXDETECTRXLB Trigger Debug Control
  
  The link starts writing debug data based on the following conditions:
   - Link_state and sub_state match the link_state_trigger and sub_state_trigger field, respectively
   - Assertion of pipe_TxDetectRxLoopbk
 RW 0x0
25 pipe_rxlecidle_trigger 
PIPE RXELECIDLE Trigger Debug Control
  
  The link start writing debug data based on the following conditions:
   - Link_state and sub_state match the link_state_trigger and sub_state_trigger field, respectively
   - Change state of pipe_RxElecIdle
 RW 0x0
24 pipe_phystatus_trigger 
PIPE PHYSTATUS Trigger Debug Control
  
  The link start writing debug data based on the following conditions:
   - Link_state and sub_state match the link_state_trigger and sub_state_trigger field, respectively
   - Assertion of pipe_PhyStatus
 RW 0x0
23:20 sub_state_trigger 
Sub-state Trigger
 RW 0x0
19:16 link_state_trigger 
Link State Trigger
 RW 0x0
15:12 peri_rsc_rxfifo_number 
Periodic Resource RXFIFO Number
 RW 0x0
11:8 peri_rsc_txfifo_number 
Periodic Resource TXFIFO Number
 RW 0x0
7:4 rxfifo_number 
RXFIFO Number
 RW 0x0
3:0 txfifo_number 
TXFIFO Number
 RW 0x0