LCSRPTMDEBUG2

         LCSRPTMDELAY2 REGISTER : This register stores LSM t4 value
  
  In Host mode this register read value is 32'h0.


Module Instance	Base Address	Register Address
`i_usb31_0__ahb_slave__11000000__DWC_usb31_block_link__SEG_L4_AHB_USB1_0x0_0x100000`	`0x1100D000`	`0x1100D074`

Size: 32

Offset: 0x74

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RESERVED_31_17` `RO 0x0`															`LDM_T4` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`LDM_T4` `RO 0x0`

LCSRPTMDEBUG2 Fields

Bit Name Description Access Reset

31:17

Bit	Name	Description	Access	Reset
31:17	`RESERVED_31_17`	Reserved	`RO`	`0x0`
16:0	`LDM_T4`	LDM_T4 This is the 't4' timestamp, which is the time the link receives the LMP TS response. The unit of this field is nanosecond (ns). Note: - The internal RTL timer counts down 125000 to 0, and restarts at 125000 (therefore, t1 > t4, except the case of roll over) - This value does not take into account the internal RTL RX pipeline delay. RTL uses this formula for adjusting 't4' based on the pipeline delay: RX_PATH_DELAY(tIsochTimestampGranularity) = (gen1 ? 4 : 5) + LPTMDPDELAY[7:4]	`RO`	`0x0`

RESERVED_31_17

Reserved

RO

0x0

16:0

LDM_T4

LDM_T4
  
  This is the 't4' timestamp, which is the time the link receives the LMP TS response.
  
  The unit of this field is nanosecond (ns).
  
  Note:
   - The internal RTL timer counts down 125000 to 0, and restarts at 125000 (therefore, t1 > t4, except the case of roll over)  
   - This value does not take into account the internal RTL RX pipeline delay.  RTL uses this formula for adjusting 't4' based on the pipeline delay:
  RX_PATH_DELAY(tIsochTimestampGranularity) = (gen1 ? 4 : 5) + LPTMDPDELAY[7:4]

RO

0x0