LCSRPTMDEBUG1 

         LCSRPTMDEBUG1 REGISTER: This register stores LDM t1 and LDM t32 values 
  
  In Host mode this register read value is 32'h0.
Module Instance Base Address Register Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_link__SEG_L4_AHB_USB1_0x0_0x100000 0x1100D000 0x1100D070

Size: 32

Offset: 0x70

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED_31_30

RO 0x0

LDM_T32

RO 0x0

LDM_T1

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LDM_T1

RO 0x0

LCSRPTMDEBUG1 Fields

Bit Name Description Access Reset
31:30 RESERVED_31_30 
Reserved
 RO 0x0
29:17 LDM_T32 
LDM_T32
  
  This is Response Delay value captured from the LMP TS response field. The unit of this field is tIsochTimestampGranularity
 RO 0x0
16:0 LDM_T1 
LDM_T1
  
  This is the 't1' timestamp, which is the time the link transmits the LMP TS request.
  
  The unit of this field is nanosecond (ns).
  
  Note:
   - The internal RTL timer counts down from 125000 to 0, and restarts at 125000 (therefore, t1 > t4, except in case of a roll over).  
   - This value does not take into account the internal RTL TX pipeline delay.  RTL uses the following formula for adjusting 't1' based on the pipeline delay:
  TX_PATH_DELAY (tIsochTimestampGranularity) = (gen1 ? 2 : 2) + LPTMDPDELAY[3:0]
 RO 0x0