GDBGLTSSM 

         Global Debug LTSSM Register
  
  Note: GDBGLTSSM register is not applicable for USB 2.0-only mode.
   - Bit Bash test should not be done on this debug register.
Module Instance Base Address Register Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_link__SEG_L4_AHB_USB1_0x0_0x100000 0x1100D000 0x1100D050

Size: 32

Offset: 0x50

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved_31_31

RO 0x0

RxElecidle

RO 0x1

reserved1

RO 0x0

LTDBTIMEOUT

RO 0x0

LTDBLINKSTATE

RO 0x4

LTDBSUBSTATE

RO 0x0

ELASTICBUFFERMODE

RO 0x0

TXELECLDLE

RO 0x1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RXPOLARITY

RO 0x0

TxDetRxLoopback

RO 0x0

LTDBPhyCmdState

RO 0x0

POWERDOWN

RO 0x2

RXEQTRAIN

RO 0x0

TXDEEMPHASIS

RO 0x1

LTDBClkState

RO 0x0

TXSWING

RO 0x0

RXTERMINATION

RO 0x0

TXONESZEROS

RO 0x0

GDBGLTSSM Fields

Bit Name Description Access Reset
31 reserved_31_31 
Reserved_31_31
 RO 0x0
30 RxElecidle 
RxElecidle
  
  For description of RxElecIdle, see table 5-4, "Status Interface Signals" of the PIPE4 Specification.
 RO 0x1
29:27 reserved1 
Reserved
 RO 0x0
26 LTDBTIMEOUT 
LTDB Timeout (LTDBTimeout)
 RO 0x0
25:22 LTDBLINKSTATE 
LTDB Link State (LTDBLinkState)
 RO 0x4
21:18 LTDBSUBSTATE 
LTDB Sub-State (LTDBSubState)
 RO 0x0
17 ELASTICBUFFERMODE 
Elastic Buffer Mode (ElasticBufferMode)
  
  For field definition, refer to Table 5-3 of the PIPE specification.
 RO 0x0
16 TXELECLDLE 
Tx Elec Idle (TxElecIdle)
  
  For field definition, refer to Table 5-3 of the PIPE specification.
 RO 0x1
15 RXPOLARITY 
Rx Polarity (RxPolarity)
  
  For field definition, refer to Table 5-3 of the PIPE specification.
 RO 0x0
14 TxDetRxLoopback 
Tx Detect Rx/Loopback (TxDetRxLoopback)
  
  For field definition, refer to Table 5-3 of the PIPE specification.
 RO 0x0
13:11 LTDBPhyCmdState 
LTSSM PHY command State (LTDBPhyCmdState)
   - 000: PHY_IDLE (PHY command state is in IDLE. No PHY request pending)
   - 001: PHY_DET (Request to start Receiver detection)
   - 010: PHY_DET_3 (Wait for Phy_Status (Receiver detection))
   - 011: PHY_PWR_DLY (Delay Pipe3_PowerDown P0 -> P1/P2/P3 request)
   - 100: PHY_PWR_A (Delay for internal logic)
   - 101: PHY_PWR_B (Wait for Phy_Status(Power state change request))
 RO 0x0
10:9 POWERDOWN 
POWERDOWN (PowerDown)
  
  For field definition, refer to Table 5-3 of the PIPE Specification.
 RO 0x2
8 RXEQTRAIN 
RxEq Train
  
  For field definition, refer to Table 5-3 of the PIPE Specification.
 RO 0x0
7:6 TXDEEMPHASIS 
TXDEEMPHASIS (TxDeemphasis)
  
  For field definition, refer to Table 5-3 of the PIPE Specification.
 RO 0x1
5:3 LTDBClkState 
LTSSM Clock State (LTDBClkState)  
  
  In multi-port host configuration, the port number is defined by Port-Select[3:0] field in the GDBGFIFOSPACE register.  Note: GDBGLTSSM register is not applicable for USB 2.0-only mode. 
   - 000: CLK_NORM (PHY is in non-P3 state and PCLK is running)    
   - 001: CLK_TO_P3 (P3 entry request to PHY);
   - 010: CLK_WAIT1 (Wait for Phy_Status (P3 request));          
   - 011: CLK_P3 (PHY is in P3 and PCLK is not running);
   - 100: CLK_TO_P0 (P3 exit request to PHY);          
   - 101: CLK_WAIT2 (Wait for Phy_Status (P3 exit request))
 RO 0x0
2 TXSWING 
Tx Swing (TxSwing)
  
  For field definition, refer to Table 5-3 of the PIPE Specification.
 RO 0x0
1 RXTERMINATION 
Rx Termination (RxTermination)
  
  For details on `DWC_USB31_PIPE_RXTERM_RESET_VAL, refer to <workspace>/src/DWC_usb31_params.svh
 RO 0x0
0 TXONESZEROS 
Tx Ones/Zeros (TxOnesZeros)
  
  For field definition, refer to Table 5-3 of the PIPE Specification.
 RO 0x0