GUSB3PIPECTL 

         Global USB 3.1 PIPE Control Register
  
  The application uses this register to configure the USB 3.1 PHY and PIPE interface.
  
  Device-only configuration requires only one register. In Host mode, registers are implemented for each port.
  
  Note:
   - For more details on the GUSB3PIPECTLn bits, refer to section <link:ext>DWC_usb31_user:GUSB3PIPECTLn_UG,"GUSB3PIPECTLn"</link> in the <link:ext>DWC_usb31_user:Title,User Guide</link>.
   - GUSB3PIPECTLn registers are not applicable for USB 2.0-only mode.
Module Instance Base Address Register Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_gbl__SEG_L4_AHB_USB1_0x0_0x100000 0x1100C100 0x1100C100

Size: 32

Offset: 0x

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PHYSoftRst

RW 0x0

HstPrtCmpl

RW 0x0

U2P3ok

RW 0x0

DisRxDetP3

RW 0x0

Ux_exit_in_Px

RW 0x0

ping_enhancement_en

RW 0x0

u1u2exitfail_to_recov

RW 0x0

request_p1p2p3

RW 0x1

StartRxDetU3RxDet

WO 0x0

DisRxDetU3RxDet

RW 0x0

DelayP1P2P3

RW 0x0

DELAYP1TRANS

RW 0x0

SUSPENDENABLE

RW 0x1

DATWIDTH

RO 0x1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATWIDTH

RO 0x1

AbortRxDetInU2

RW 0x0

SkipRxDet

RW 0x0

LFPSP0Algn

RW 0x1

P3P2TranOK

RW 0x0

P3ExSigP2

RW 0x0

LFPSFILTER

RW 0x0

RX_DETECT_to_Polling_LFPS_Control

RW 0x1

reserved_7

RW 0x0

TX_SWING

RW 0x0

TX_MARGIN

RW 0x0

SS_TX_DE_EMPHASIS

RW 0x1

ELASTIC_BUFFER_MODE

RW 0x0

GUSB3PIPECTL Fields

Bit Name Description Access Reset
31 PHYSoftRst 
USB 3.1 PHY Soft Reset 
  
  PHY soft-reset; to issue PHY reset, software should set this bit and reset this bit after meeting PHY reset timing.
RW 0x0
30 HstPrtCmpl 
HstPrtCmpl
  
  This feature tests the PIPE PHY compliance patterns without having to have a test fixture on the USB 3.1 cable. 
  
  This bit enables placing the SS port link into a compliance state.
  
  In compliance lab testing, the SS port link enters compliance after failing the first polling sequence after power on. Set this bit to 0, when you run compliance tests.
  
  The sequence for using this functionality is as follows:
   - 1. Disconnect any plugged in devices.
   - 2. Perform USBCMD.HCRST or power-on-chip reset.
   - 3. Set PORTSC.PP=0.
   - 4. Set GUSB3PIPECTL. HstPrtCmpl=1. This places the link into compliance state.
  To advance the compliance pattern, follow this sequence (toggle the set GUSB3PIPECTL. HstPrtCmpl):
   - 1. Set GUSB3PIPECTL.HstPrtCmpl=0.
   - 2. Set GUSB3PIPECTL.HstPrtCmpl=1. This advances the link to the next compliance pattern.
  To exit from the compliance state perform USBCMD.HCRST or power-on-chip reset.
RW 0x0
29 U2P3ok 
Enable P3 entry during U2/SSInactive (U2P3ok). This is not recommended with Synopsys PHY which has P3 exit time of ~1ms and P2 exit time of ~100uS. This is recommended only if your PHYs P3 exit time is close to P2 exit time. Putting the ESS PHY in P3 during U2 would affect ESS Asynchronous endpoint performance and also this could prevent U2 entry if there are ESS periodic endpoints and their BInterval is in the sub milli-second range.
  rammer's Guide for more details.
   - 0: During link state U2/ESS.Inactive, put PHY in P2 (Default)
   - 1: During link state U2/ESS.Inactive, put PHY in P3 (Not recommended for Synopsys PHY).  
  Note: For a port, if GUSB3PIPECTL[7]=1 and GUSB3PIPECTL[29]=1, set GUSB3PIPECTL[11] to 1.
 RW 0x0
28 DisRxDetP3 
Disabled receiver detection in P3 (DisRxDetP3)
   - 0: If PHY is in P3 and controller needs to perform receiver detection, The controller performs receiver detection in P3.
   - 1: If PHY is in P3 and controller needs to perform receiver detection, The controller changes the PHY power state to P2 and then performs receiver detection. After receiver detection, the cores changes PHY power state to P3.
 RW 0x0
27 Ux_exit_in_Px 
Ux Exit in Px (Ux_exit_in_Px)
   - 0: The controller does U1/U2/U3 exit in PHY power state P0.
   - 1: The controller does U1/U2/U3 exit in PHY power state P1/P2/P3 respectively.  
  This bit is added for SS PHY workaround where SS PHY injects a glitch on pipe_RxElecIdle while receiving Ux exit LFPS, and pipe_PowerDown change is in progress.
  
  Note: This bit is used by third-party SS PHY. It must be set to '0' for Synopsys PHY.
 RW 0x0
26 ping_enhancement_en 
Ping Enhancement Enable (ping_enhancement_en)
  
  When set, the Downstream port U1 ping receive timeout becomes 500 ms instead of 300 ms. Minimum Ping.LFPS receive duration is 8 ns (one mac31_clk). This field is valid for the downstream port only. 
  
  Note: This bit is used by third-party SS PHY. It must be set to '0' for Synopsys PHY.
RW 0x0
25 u1u2exitfail_to_recov 
U1U2exitfail to Recovery (u1u2exitfail_to_recov)
  
  When set, and U1/U2 LFPS handshake fails, the LTSSM transitions from U1/U2 to Recovery instead of SS Inactive. If Recovery fails, then the LTSSM can enter SS.Inactive. This is an enhancement only. It prevents interoperability issue if the remote link does not do proper handshake.
 RW 0x0
24 request_p1p2p3 
Always Request P1/P2/P3 for U1/U2/U3 (request_p1p2p3)
  
  When set, the controller always requests PHY power change from P0 to P1/P2/P3 during U0 to U1/U2/U3 transition.
  
  If this bit is 0, and immediate Ux exit (remotely initiated, or locally initiated) happens, the controller does not request P1/P2/P3 power state change.
  
  Note: This bit must be set to '1' for Synopsys PHY. For third-party SS PHY, check with your PHY vendor.
 RW 0x1
23 StartRxDetU3RxDet 
Start Receiver Detection in U3/Rx.Detect (StartRxdetU3RxDet)
  
  If DWC_USB31_GUSB3PIPECTL_INIT[22] is set, and the link is in either U3 or Rx.Detect state, the controller starts receiver detection on the rising edge of this bit. This can only be used for Downstream ports. This bit must be set to '0' for Upstream ports. This feature must not be enabled for normal operation. If have to use this feature, contact Synopsys.
 WO 0x0
22 DisRxDetU3RxDet 
Disable Receiver Detection in U3/Rx.Det
  
  When set, the controller does not handle receiver detection in either U3 or Rx.Detect states. DWC_USB31_GUSB3PIPECTL_INIT[23] must be used to start receiver detection manually. This bit can only be used for the downstream port. This bit must be set to "0" for Upstream ports. This feature must not be enabled for normal operation. If you have to use this feature, contact Synopsys.
 RW 0x0
21:19 DelayP1P2P3 
Delay P1P2P3
  
  Delay P0 to P1/P2/P3 request when entering U1/U2/U3 until (DWC_USB31_GUSB3PIPECTL_INIT[21:19]*8) 8B10B error occurs, or Pipe3_RxValid drops to 0.
  
  DWC_USB31_GUSB3PIPECTL_INIT[18] must be 1 to enable this functionality.
 RW 0x0
18 DELAYP1TRANS 
Delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively.
   - 1'b1: When entering U1/U2/U3, delay the transition to P1/P2/P3 until the pipe signals, pipe_RxElecIdle is 1 and pipe_RxValid is 0
   - 1'b0: When entering U1/U2/U3, transition to P1/P2/P3 without checking for pipe_RxElecIdle and pipe_RxValid.
  Note: This bit should be set to 0 for Synopsys USB 3.1 PHY.
 RW 0x0
17 SUSPENDENABLE 
Suspend USB 3.1 ESS PHY (Suspend_en)
  
  When set, and if Suspend conditions are valid, the USB 3.1 PHY enters Suspend mode.
  
  For DRD configurations, it is recommended that this bit is set to '0' during coreConsultant configuration. If it is set to '1', then the application must clear this bit after power-on reset. Application needs to set it to '1' after the controller initialization is completed.
  
  If software is not going to change the controller from device to host mode or vice versa after power-on reset, then the software does not need to clear this bit. This ensures that the PHY clock is available when the software changes the GCTL.PRTCAPDIR register field.
  
  For all other configurations, this bit can be set to '1' during controller configuration. Must be 1 if need special support of P3, P3.CPM and P4 in several LTSSM states.
 RW 0x1
16:15 DATWIDTH 
PIPE Data Width (DatWidth)
   - 2'b00: 32 bits
   - 2'b01: 16 bits
   - 2'b10: 8 bits
  One clock after reset, these bits receive the value seen on the pipe_DataBusWidth. The simulation testbench uses the coreConsultant parameter to configure the VIP. These bits in the coreConsultant parameter must match your PHY data width and the pipe_DataBusWidth port.
 RO 0x1
14 AbortRxDetInU2 
Abort Rx Detect in U2 (AbortRxDetInU2)
  
  When set, and the link state is U2, then the controller will abort receiver detection if it receives U2 exit LFPS from the remote link partner. This bit is for the downstream port only.
  
  Note: This bit is used by third-party SS PHY. It must be set to '0' for Synopsys PHY.
RW 0x0
13 SkipRxDet 
Skip Rx Detect:
  
  When set, the controller skips Rx Detection if pipe_RxElecIdle is low. 
  
  Skip is defined as waiting for the appropriate timeout, then repeating the operation.
RW 0x0
12 LFPSP0Algn 
LFPS P0 Align
  
  When this bit is set, LFPS during U1/U2/U3 exit is extended until data is ready at the PIPE to ensure the 20-ns gap between LFPS and SS/SSP.
RW 0x1
11 P3P2TranOK 
P3 P2 Transitions OK (P3P2TranOK)
  
  When set, the controller transitions directly from Phy power state P2 to P3 or from state P3 to P2.
  When not set, P0 is always entered as an intermediate state during transitions between P2 and P3, as defined in the PIPE4 Specification.
  
  According to the PIPE4 Specification, any direct transition between P3 and P2 is illegal. This bit is used only for some non-Synopsys PHYs that cannot do LFPS in P3.
  
  Note: This bit is used by third-party SS PHY. It must be set to '0' for Synopsys PHY.
 RW 0x0
10 P3ExSigP2 
P3 Exit Signal in P2 (P3ExSigP2)
  
  When this bit is set, the controller always changes the PHY power state to P2, before attempting a U3 exit handshake.
  
  Note: This bit is used by third-party SS PHY. It must be set to '0' for Synopsys PHY.
 RW 0x0
9 LFPSFILTER 
LFPS Filter (LFPSFilt)
  
  When set, filter LFPS reception with pipe_RxValid in PHY power state P0, that is, ignore LFPS reception from the PHY unless both pipe_Rxelecidle and pipe_RxValid are deasserted.
 RW 0x0
8 RX_DETECT_to_Polling_LFPS_Control 
RX_DETECT to Polling.LFPS Control
   - 1'b0: Enables a 400us delay to start Polling LFPS after RX_DETECT. This allows VCM offset to settle to a proper level.
   - 1'b1: Disables the 400us delay to start Polling LFPS after RX_DETECT.
  During controller certification with third party PHY it is observed that the PHY is not able to meet the Tx AC common mode voltage active (VTX-CM-ACPP_ACTIVE <100mv) if the link starts polling within 80us from the time rx.detect is performed.
  
  To meet this VTX-CM-ACPP_ACTIVE specification, the polling must be delayed further. If the PHY does not have issue then they can set this bit to 1 which allows polling to start within 80us.
 RW 0x1
7 reserved_7 
Reserved
 RW 0x0
6 TX_SWING 
Tx Swing (TxSwing)
  
  Refer to the PIPE Specification.
 RW 0x0
5:3 TX_MARGIN 
Tx Margin[2:0] (TxMargin)
  
  Refer to Table 5-3 of the PIPE4 Specification.
 RW 0x0
2:1 SS_TX_DE_EMPHASIS 
Tx Deemphasis (TxDeemphasis)
  
  The value driven to the PHY is controlled by the LTSSM during USB 3.1 Compliance mode.
  
  (Refer to Table 5-3 of the PIPE Specification.)
 RW 0x1
0 ELASTIC_BUFFER_MODE 
Elastic Buffer Mode (ElasticBufferMode)
  
  (Refer to Table 5-3 of the PIPE Specification.)
 RW 0x0