GUSB2RHBCTL 

         Global USB2 Root Hub Control Register
  
  In Host mode, per-port registers are implemented.
Module Instance Base Address Register Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_gbl__SEG_L4_AHB_USB1_0x0_0x100000 0x1100C100 0x1100C100

Size: 32

Offset: 0x

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved_31_20

RO 0x0

OVRD_FS_INT_PKT_DEL

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OVRD_FS_INT_PKT_DEL

RW 0x0

OVRD_HS_INT_PKT_DEL

RW 0x0

OVRD_L1TIMEOUT

RW 0x0

GUSB2RHBCTL Fields

Bit Name Description Access Reset
31:20 Reserved_31_20 
Reserved
 RO 0x0
19:12 OVRD_FS_INT_PKT_DEL 
Overriding the internal FS interpacket delay.
  
  This field indicates the value of Tx-to-Tx packet gap for FS devices. The encoding is as follows:
   - 0: The FS Tx-to-Tx interpacket delay is calculated internally. This value is not used.
   - Non-0: The FS Tx-to-Tx interpacket delay is OVRD_FS_INT_PKT_DEL number of UTMI clocks.
  Note:
   - This field is applicable only in Host mode.
   - For normal operation (to work with most FS devices), no change is required to this field.
   - The programmable FS device Tx-to-Tx interpacket delay is provided to support any legacy FS devices that might require different delays than the default/fixed ones.
   - Include your PHY delays when programming this value. For example, if your PHY TxEndDelay in FS mode is five UTMI/ULPI clocks, then subtract this delay from the delay requirement of the device.
 RW 0x0
11:4 OVRD_HS_INT_PKT_DEL 
Overriding the internal HS interpacket delay.
  
  This field indicates the value of Tx-to-Tx packet gap for HS devices. The encoding is as follows:
   - 0: The HS Tx-to-Tx interpacket delay is calculated internally. This value is not used.
   - Non-0: The HS Tx-to-Tx interpacket delay is OVRD_HS_INT_PKT_DEL number of UTMI clocks. This will also override the TX_IPGAP_LINECHECK_DIS setting.
  Note:
   - This field is applicable only in Host mode.
   - For normal operation (to work with most HS devices), no change is required to this field.
   - When this is set to a non-0 value, it is required to set the TX_IPGAP_LINECHECK_DIS to 0.
   - The programmable HS device Tx-to-Tx interpacket delay is provided to support any legacy HS devices that might require different delays than the default/fixed ones.
   - Include your PHY delays when programming this value. For example, if your PHY TxEndDelay in HS mode is five UTMI/ULPI clocks, then subtract this delay from the delay requirement of the device.
 RW 0x0
3:0 OVRD_L1TIMEOUT 
Overriding the driver programmed L1TIMEOUT value.
  
  If this value is 0, the L1 Timeout value is taken from the xHCI PORTHLPMC register. If this value is non-0, then this will override the L1 Timeout value programmed in the xHCI PORTHLPMC register. In that case the actual L1 Timeout would be 2 ^ <OVRD_L1TIMEOUT-1> * 8us. (1=8us, 2=16us, 3=32us etc)
 RW 0x0