GUSB2PHYCFG

UTMI PHY Soft Reset (PHYSoftRst)
  
  Causes the usb2phy_reset signal to be asserted to reset a UTMI PHY. Not applicable to ULPI because ULPI PHYs are reset via their FunctionControl.Reset register, and the controller automatically writes to this register when the controller is reset (vcc_reset_n, USBCMD.HCRST, DCTL.SoftReset, or GCTL.SoftReset)

Reserved_30

ULPI_LPM_WITH_OPMODE_CHK
  
  Support the LPM over ULPI without NOPID token to the ULPI PHY. 
  
  If this bit is set, the ULPI PHY is expected to qualify the EXT PID with OPMODE=2'b00 for LPM and not treat it as a NOPID. Check with your PHY vendor about your PHY behavior. This bit is valid only when the DWC_USB31_HSPHY_INTERFACE parameter is 2 or 3.
   - 1'b0: A NOPID is sent before sending an EXTPID for LPM; 
   - 1'b1: An EXTPID is sent without previously sending a NOPID; 
  Note: This bit is valid only in host mode. This bit should be '0' for Synopsys PHY.
  

HSIC_CON_WIDTH_ADJ
  
  This bit is used in the HSIC device mode of operation. It can be used to control the connect duration. 
  
  The encoding is as follows:
   - 0: 3 times the strobe period
   - 1: 4 times the strobe period
   - 2: 5 times the strobe period
   - 3: 6 times the strobe period

INV_SEL_HSIC
  
  The application driver uses this bit to control the HSIC enable/disable function. When set to '1', this bit overrides and functionally inverts the "if_select_hsic" input signal.
  If {INV_SEL_HSIC, if_select_hsic} is: 
   - 00: HSIC Capability is disabled.
   - 01: HSIC Capability is enabled.
   - 10: HSIC Capability is enabled.
   - 11: HSIC Capability is disabled.
  If the controller operates as non-HSIC-capable, it can only connect to non-HSIC-capable PHYs. If it operates as HSIC-capable, it can connect to HSIC-capable PHYs.
  
  This bit is reserved if the DWC_USB31_ENABLE_HSIC parameter is set to '0'. When selecting the HSIC feature, set the host side to HSIC mode first, then set the device mode side. If the device side is set to HSIC mode first and if the host does not see a connection in HSIC mode, then you must de-select the device HSIC mode and select it again using the if_select_hsic setting or register bit GUSB2PHYCFGn[26] to ensure that the device can connect to the host.

Overriding the FS/LS disconnect time to 32us.
  
  If this value is 0, the FS/LS disconnect time is set to 2.5us as per the USB specification. If this value is non-0, then the disconnect detection time is set to 32us.
  
  Normally this value is set to 0. But if the 2.0 PHYs introduce noise on UTMI linestate and cause SE0 gliches longer than 2.5us, then a false disconnect condition may get triggered. To avoid interoperability issues with these PHYs, this bit can be set to 1

LS Turnaround Time (LSTRDTIM)
  
  This field indicates the value of the Rx-to-Tx packet gap for LS devices. The encoding is as follows:
   - 0: 2 bit times
   - 1: 2.5 bit times
   - 2: 3 bit times
   - 3: 3.5 bit times
   - 4: 4 bit times
   - 5: 4.5 bit times
   - 6: 5 bit times
   - 7: 5.5 bit times
  Note: 
   - This field is applicable only in Host mode.
   - For normal operation (to work with most LS devices), it is recommended to set the value of this field to 3'h0 (2 bit times).
   - The programmable LS device inter-packet gap and turnaround delays are provided to support some legacy LS devices that might require different delays than the default/fixed ones. For instance, the AOpen LS mouse requires 3 bit times of inter-packet gap to work correctly.
   - Include your PHY delays when programming the LSIPD/LSTRDTIM values. For example, if your PHY TxEndDelay in LS mode is 30 UTMI/ULPI CLKs, then subtract this delay (~1 LS bit time) from the delay requirement of the device.

LS Inter-Packet Time (LSIPD)
  
  This field indicates the value of Tx-to-Tx packet gap for LS devices. The encoding is as follows: 
   - 0: 2 bit times
   - 1: 2.5 bit times
   - 2: 3 bit times
   - 3: 3.5 bit times
   - 4: 4 bit times
   - 5: 4.5 bit times
   - 6: 5 bit times
   - 7: 5.5 bit times
  Note:
   - This field is applicable only in Host mode.
   - For normal operation (to work with most LS devices), it is recommended to set this field to 3'h2 (3 bit times).
   - The programmable LS device inter-packet gap and turnaround delays are provided to support some legacy LS devices that might require different delays than the default/fixed ones. For instance, the AOpen LS mouse requires 3 bit times of inter-packet gap to work correctly.
   - Include your PHY delays when programming the LSIPD/LSTRDTIM values. For example, if your PHY TxEndDelay in LS mode is 30 UTMI/ULPI CLKs, then subtract this delay (~1 LS bit time) from the delay requirement of the device.

ULPI External VBUS Indicator (ULPIExtVbusIndicator)
  
  Indicates the ULPI PHY VBUS indicator.
   - 1'b0: PHY uses an internal VBUS valid comparator.
   - 1'b1: PHY uses an external VBUS valid comparator.
  Valid only when RTL parameter DWC_USB31_HSPHY_INTERFACE = 2 or 3

ULPI External VBUS Drive (ULPIExtVbusDrv)
  
  Selects supply source to drive 5V on VBUS, in the ULPI PHY.
   - 1'b0: PHY drives VBUS with internal charge pump
   - 1'b1: PHY drives VBUS with an external supply
  (Only when RTL parameter DWC_USB31_HSPHY_INTERFACE = 2 or 3)

Reserved

ULPI Auto Resume (ULPIAutoRes)
  
  This field is valid for host mode only.
  
  Sets the AutoResume bit in Interface Control register on the ULPI PHY.
   - 1'b0: PHY does not use the AutoResume feature.
   - 1'b1: PHY uses the AutoResume feature.
  Valid only when RTL parameter DWC_USB31_HSPHY_INTERFACE = 2 or 3

eUSB 2.0 UTMI interface enhancement (eUSB2OPMODE)
  
  This field is valid in host mode of operation.
  
   If this bit is set opmode and utmi_txvalid change on same clock when opmode switches to 2 for test mode operation. 
   - 1'b0: eUSB UTMI interface enhancement disabled.
   - 1'b1: eUSB UTMI interface enhancement enabled.

USB 2.0 Turnaround Time (USBTrdTim)
  
  Sets the turnaround time in PHY clocks.
  
  Specifies the response time for a MAC request to the Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM).
  
  The following are the required values for the minimum SoC bus frequency of 60 MHz. USB turnaround time is a critical certification criteria when using long cables and five hub levels.
  
  The required values for this field:
   - 4'h5: When the MAC interface is 16-bit UTMI+.
   - 4'h9: When the MAC interface is 8-bit UTMI+/ULPI.
  If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger value.
  
  Note: This field is valid only in device mode.

Transceiver Delay:  
  
  Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertion of the TxValid signal during a HS Chirp.
  
  When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the time when the Transceiver Select is set to 2'b00 (HS) to the time the TxValid is driven to 1 for sending the chirp-K. This delay is required for some UTMI/ULPI PHYs.
  
  Note: 
   - If you enable the hibernation feature when the device controller comes out of power-off, you must re-initialize this bit with the appropriate value because the controller does not save and restore this bit value during hibernation. 
   - This bit is valid only in device mode.

Enable utmi_sleep_n and utmi_l1_suspend_n 
  
  The application uses this bit to control utmi_sleep_n and utmi_l1_suspend_n assertion to the PHY in the L1 state.
   - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the controller is not transferred to the external PHY.
   - 1'b1: utmi_sleep_n and utmi_l1_suspend_n assertion from the controller is transferred to the external PHY.
  Note: In Device mode - Before issuing any device endpoint command when operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a command is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get completed.

USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select 
  
  The application uses this bit to select a high-speed PHY or a full-speed transceiver.
   - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access.
   - 1'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access.
  If both interface types are selected in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface is active, with Read-Write bit access.

Suspend USB2.0 HS/FS/LS PHY 
  
  When set, USB 2.0 PHY enters Suspend mode if Suspend conditions are valid.
  
  For DRD configurations, it is recommended that this bit is set to 0 during coreConsultant configuration. If it is set to 1, then the application must  clear this bit after power-on reset. Application needs to set it to 1 after the controller initialization completes.
  
  If software is not going to change the controller from device to host mode or vice versa after power-on reset, then the software does not need to clear this bit. This ensures that the PHY clock is available when the software changes the GCTL.PRTCAPDIR register field.
  
  For all other configurations, this bit can be set to 1 during controller configuration.
  
  Note: In Device mode, before issuing any device endpoint command when operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a command is issued when the device is in L2 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get completed.

Full-Speed Serial Interface Select (FSIntf)
  
  The application uses this bit to select a unidirectional or bidirectional USB 1.1 full-speed serial transceiver interface.
   - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with Read Only access.
   - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access.
  Note: USB 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0.

ULPI or UTMI+ Select (ULPI_UTMI_Sel)
  
  The application uses this bit to select a UTMI+ or ULPI Interface.
   - 1'b0: UTMI+ Interface
   - 1'b1: ULPI Interface
  This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreConsultant configuration (DWC_USB31_HSPHY_INTERFACE = 3). 
  Otherwise, this bit is read-only and the value depends on the interface selected through DWC_USB31_HSPHY_INTERFACE.

PHY Interface (PHYIf)
  
  If UTMI+ is selected, the application uses this bit to configure the controller to support a UTMI+ PHY with an 8- or 16-bit interface.
   - 1'b0: 8 bits
   - 1'b1: 16 bits
  ULPI Mode: 1'b0
  
  Note:
   - All the enabled 2.0 ports must have the same clock frequency as Port0 clock frequency (utmi_clk[0]).
   - The UTMI 8-bit and 16-bit modes cannot be used together for different ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time).
   - If any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz.

HS/FS Timeout Calibration (TOutCal)
  
  The number of PHY clocks, as indicated by the application in this field, is multiplied by a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the controller to account for additional delays introduced by the PHY. This may be required, since the delay introduced by the PHY in generating the linestate condition may vary among PHYs.
  
  The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this field based on the speed of connection. The number of bit times added per PHY clock are:
  
  High-speed operation:
   - One 30-MHz PHY clock = 16 bit times
   - One 60-MHz PHY clock = 8 bit times
  Full-speed operation:
   - One 30-MHz PHY clock = 0.4 bit times
   - One 60-MHz PHY clock = 0.2 bit times
   - One 48-MHz PHY clock = 0.25 bit times