GTXFIFOSIZ7

         Register GTXFIFOSIZ 7


Module Instance	Base Address	Register Address
`i_usb31_0__ahb_slave__11000000__DWC_usb31_block_gbl__SEG_L4_AHB_USB1_0x0_0x100000`	`0x1100C100`	`0x1100C11C`

Size: 32

Offset: 0x1C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`TXFSTADDR_N` `RW 0x110B`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`reserved_15` `RO 0x0`	`TXFDEP_N` `RW 0x105`

GTXFIFOSIZ7 Fields

Bit Name Description Access Reset

31:16

Bit	Name	Description	Access	Reset
31:16	`TXFSTADDR_N`	Transmit FIFOn RAM Start Address This field contains the memory start address for TxFIFOn in MDWIDTH-bit words.	`RW`	`0x110B`
15	`reserved_15`	Reserved	`RO`	`0x0`
14:0	`TXFDEP_N`	TXFDEP_N This field contains the depth of TxFIFOn in MDWIDTH-bit words. - Minimum value: 32 - Maximum value: 32,767 For more information, see in the <link:ext>DWC_usb31_databook:rx_tx_fifo_config,"Rx/Tx FIFO Configuration"</link> section in the <link:ext>DWC_usb31_databook:Title,Databook</link>.	`RW`	`0x105`

TXFSTADDR_N

Transmit FIFOn RAM Start Address 
  
  This field contains the memory start address for TxFIFOn in MDWIDTH-bit words.

RW

0x110B

reserved_15

Reserved

RO

0x0

14:0

TXFDEP_N

TXFDEP_N
  
  This field contains the depth of TxFIFOn in MDWIDTH-bit words.
   - Minimum value: 32
   - Maximum value: 32,767
  For more information, see in the  <link:ext>DWC_usb31_databook:rx_tx_fifo_config,"Rx/Tx FIFO Configuration"</link> section in the <link:ext>DWC_usb31_databook:Title,Databook</link>.

RW

0x105