GTXFIFOSIZ15

         Register GTXFIFOSIZ 15


Module Instance	Base Address	Register Address
`i_usb31_0__ahb_slave__11000000__DWC_usb31_block_gbl__SEG_L4_AHB_USB1_0x0_0x100000`	`0x1100C100`	`0x1100C13C`

Size: 32

Offset: 0x3C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`TXFSTADDR_N` `RW 0x1264`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`reserved_15` `RO 0x0`	`TXFDEP_N` `RW 0xC`

GTXFIFOSIZ15 Fields


Bit	Name	Description	Access	Reset
31:16	`TXFSTADDR_N`	TXFSTADDR_N	`RW`	`0x1264`
15	`reserved_15`	Reserved	`RO`	`0x0`
14:0	`TXFDEP_N`	TXFDEP_N	`RW`	`0xC`