GTXFIFOSIZ0

         Global Transmit FIFO Size Register
  
  This register specifies the RAM start address and depth (both in MDWIDTH-bit words) for each implemented TxFIFO. The number of TxFIFOs depends on the configuration parameters including the number of Device IN Endpoints, number of Host Bus Instances, and presence of Debug Capability.
  
  The register default values for each mode are assigned in coreConsultant based on the maximum packet size, number of packets to be buffered, speed of host bus instance, bus latency, and mode of operation (host, device, or, DBC). Upon reset and mode transitions, hardware automatically programs these registers to the default values. Consequently, there is typically no need for the software to modify the pre-defined default values.
  
  For the debug capability mode, the currently mapped EP0 IN and EP1 IN TxFIFO numbers can be read from the GFIFOPRIDBC register.


Module Instance	Base Address	Register Address
`i_usb31_0__ahb_slave__11000000__DWC_usb31_block_gbl__SEG_L4_AHB_USB1_0x0_0x100000`	`0x1100C100`	`0x1100C100`

Size: 32

Offset: 0x

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`TXFSTADDR_N` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`reserved_15` `RO 0x0`	`TXFDEP_N` `RW 0x43`

GTXFIFOSIZ0 Fields

Bit Name Description Access Reset

31:16

Bit	Name	Description	Access	Reset
31:16	`TXFSTADDR_N`	Transmit FIFOn RAM Start Address This field contains the memory start address for TxFIFOn in MDWIDTH-bit words.	`RW`	`0x0`
15	`reserved_15`	Reserved	`RO`	`0x0`
14:0	`TXFDEP_N`	TxFIFO Depth This field contains the depth of TxFIFOn in MDWIDTH-bit words. - Minimum value: 32 - Maximum value: 32,767 For more information, see in the <link:ext>DWC_usb31_databook:rx_tx_fifo_config,"Rx/Tx FIFO Configuration"</link> section in the <link:ext>DWC_usb31_databook:Title,Databook</link>.	`RW`	`0x43`

TXFSTADDR_N

Transmit FIFOn RAM Start Address 
  
  This field contains the memory start address for TxFIFOn in MDWIDTH-bit words.

RW

0x0

reserved_15

Reserved

RO

0x0

14:0

TXFDEP_N

TxFIFO Depth 
  
  This field contains the depth of TxFIFOn in MDWIDTH-bit words.
   - Minimum value: 32
   - Maximum value: 32,767
  For more information, see in the  <link:ext>DWC_usb31_databook:rx_tx_fifo_config,"Rx/Tx FIFO Configuration"</link> section in the <link:ext>DWC_usb31_databook:Title,Databook</link>.

RW

0x43