GRXFIFOSIZ4

         Register


Module Instance	Base Address	Register Address
`i_usb31_0__ahb_slave__11000000__DWC_usb31_block_gbl__SEG_L4_AHB_USB1_0x0_0x100000`	`0x1100C100`	`0x1100C110`

Size: 32

Offset: 0x10

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RXFSTADDR_N` `RW 0x826`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`reserved_15` `RO 0x0`	`RXFDEP_N` `RW 0x0`

GRXFIFOSIZ4 Fields

Bit Name Description Access Reset

31:16

Bit	Name	Description	Access	Reset
31:16	`RXFSTADDR_N`	Transmit FIFOn RAM Start Address This field contains the memory start address for TxFIFOn in MDWIDTH-bit words.	`RW`	`0x826`
15	`reserved_15`	Reserved	`RO`	`0x0`
14:0	`RXFDEP_N`	RXFDEP_N: RxFIFO Depth (RxFDep_n) This field contains the depth of RxFIFOn in MDWIDTH-bit words. - Minimum value: 32 - Maximum value: 16,384	`RW`	`0x0`

RXFSTADDR_N

Transmit FIFOn RAM Start Address 
  
  This field contains the memory start address for TxFIFOn in MDWIDTH-bit words.

RW

0x826

reserved_15

Reserved

RO

0x0

14:0

RXFDEP_N

RXFDEP_N:  RxFIFO Depth (RxFDep_n)
  
  This field contains the depth of RxFIFOn in MDWIDTH-bit words.
   - Minimum value: 32
   - Maximum value: 16,384

RW

0x0