GRXFIFOSIZ0 

         Global Receive FIFO Size Register
  
  This register specifies the RAM start address and depth (both in MDWIDTH-bit words) for each implemented RxFIFO. The number of RxFIFOs depends on the configuration parameters including the number of Host Bus Instances and presence of Debug Capability; device mode requires only one RxFIFO.
  
  The register default values for each mode are assigned in coreConsultant based on the maximum packet size, number of packets to be buffered, speed of the host bus instance, bus latency, and mode of operation (host, device, or DBC). Upon reset and mode transitions, hardware automatically programs these registers to the default values. Consequently, there is typically no need for the software to modify the pre-defined default values.
  
  For the debug capability mode, the currently mapped RxFIFO number can be read from the GFIFOPRIDBC register.
Module Instance Base Address Register Address
i_usb31_0__ahb_slave__11000000__DWC_usb31_block_gbl__SEG_L4_AHB_USB1_0x0_0x100000 0x1100C100 0x1100C100

Size: 32

Offset: 0x

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RXFSTADDR_N

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved_15

RO 0x0

RXFDEP_N

RW 0x413

GRXFIFOSIZ0 Fields

Bit Name Description Access Reset
31:16 RXFSTADDR_N 
RxFIFOn RAM Start Address (RxFStAddr_n)
  
  This field contains the memory start address for RxFIFOn in MDWIDTH-bit words.
 RW 0x0
15 reserved_15 
Reserved
 RO 0x0
14:0 RXFDEP_N 
RxFIFO Depth (RxFDep_n)
  
  This field contains the depth of RxFIFOn in MDWIDTH-bit words.
   - Minimum value: 32
   - Maximum value: 16,384
 RW 0x413