CH3_SWHSDSTREG

         Channelx Software handshake Destination Register.


Module Instance	Base Address	Register Address
`i_dma__dmac1_ahb_slv__10dc0000__Channel3_Registers_Address_Block__SEG_L4_AHB_dmac1_s_0x0_0x10000`	`0x10DC0300`	`0x10DC0340`

Size: 64

Offset: 0x40

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.


Bit Fields
63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48
`RSVD_DMAC_CHx_SWHSDSTREG_6to63` `RO 0x0`
47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
`RSVD_DMAC_CHx_SWHSDSTREG_6to63` `RO 0x0`
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RSVD_DMAC_CHx_SWHSDSTREG_6to63` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RSVD_DMAC_CHx_SWHSDSTREG_6to63` `RO 0x0`										`SWHS_LST_DST_WE` `WO 0x0`	`SWHS_LST_DST` `RW 0x0`	`SWHS_SGLREQ_DST_WE` `WO 0x0`	`SWHS_SGLREQ_DST` `RW 0x0`	`SWHS_REQ_DST_WE` `WO 0x0`	`SWHS_REQ_DST` `RW 0x0`

CH3_SWHSDSTREG Fields

Bit Name Description Access Reset

63:6

RSVD_DMAC_CHx_SWHSDSTREG_6to63

DMAC Channelx Software Handshake Destination Register (bits 6to63) Reserved bits - Read Only

RO

0x0

SWHS_LST_DST_WE

Write Enable bit for Software Handshake Last Request for Channel Destination.
Note: This bit always returns 0 on a read back.

Value	Description
0x0	Disables write to the SWHS_LAST_DST bit
0x1	Enables write to the SWHS_LAST_DST bit

WO

0x0

SWHS_LST_DST

Software Handshake Last Request for Channel Destination.
This bit is used to request LAST dma destination data transfer if software handshaking
method is selected for the destination of the corresponding channel.
This bit is ignored if software handshaking is not enabled for the destination of the Channelx or if the destination of
Channelx is not the flow controller. CHx_SWHSDstReg.SWHS_Req_Dst bit must be set to 1 for DW_axi_dmac to treat it as a valid software handshaking request.
If CHx_SWHSDstReg.SWHS_SglReq_Dst
is set to 1, the LAST request is for SINGLE dma transaction (AXI burst length = 1), else the request is treated as a BURST transaction request.
DW_axi_dmac clears this bit to 0 once software reads
CHx_SWHSDstReg.SWHS_Ack_Dst bit and sets it as 1. Software can only set this bit to 1; it is not allowed to clear this bit to 0; only DW_axi_dmac can clear this bit.
Note: SWHS_Lst_Src bit is written only if the corresponding write enable bit, SWHS_Lst_Src_WE is asserted on the same register write operation and if the Channelx is enabled in the DMAC_ChEnReg register. This allows software to set a bit in the CHx_SWHSDstReg register without performing a read-modified write operation.

Value	Description
0x0	Destination peripheral indication that the current transfer is not the last transfer
0x1	Destination peripheral indication to dmac that the current transfer is the last transfer

RW

0x0

SWHS_SGLREQ_DST_WE

Write Enable bit for Software Handshake Single Request for Channel Destination.
Note: This bit always returns 0 on a read block.

Value	Description
0x0	Disables write to the SWHS_SGLREQ_DST bit
0x1	Enables write to the SWHS_SGLREQ_DST bit

WO

0x0

SWHS_SGLREQ_DST

Software Handshake Single Request for Channel Destination.
This bit is used to request SINGLE (AXI burst length = 1) dma destination data
transfer if software handshaking method is selected for the destination of the corresponding channel.
This bit is ignored if software handshaking is not enabled for the destination of the
Channelx. The functionality of this field depends on whether the peripheral is the flow controller.
DW_axi_dmac clears this bit to 0 once software reads CHx_SWHSDstReg.SWHS_Ack_Dst bit and
sees it as 1. Software can only set this bit to 1; it is not allowed to clear this bit to 0; only DW_axi_dmac can clear this bit.
Note: SWHS_SglReq_Dst bit is written only if the corresponding write enable bit, SWHS_SglReq_Dst_WE is asserted on the same register write operation and if the Channelx is enabled in the DMAC_ChEnReg register. This allows software to set a bit in the CHx_SWHSDstReg register without performing a read-modified write operation.

Value	Description
0x0	Destination peripheral is not requesting for a single transfer
0x1	Destination peripheral request for a single dma transfer

RW

0x0

SWHS_REQ_DST_WE

Write Enable bit for Software Handshake Request for Channel Destination.
Note: This bit always returns 0 on a read block.

Value	Description
0x0	Disables write to the SWHS_REQ_DST bit
0x1	Enables write to the SWHS_REQ_DST bit

WO

0x0

SWHS_REQ_DST

Software Handshake Request for Channel Destination.
This bit is used to request dma destination data transfer if software handshaking method is
selected for the destination of the corresponding channel.
This bit is ignored if software handshaking is not enabled for the source of the Channelx. The functionality of this field depends on
whether the peripheral is the flow controller.
DW_axi_dmac clears this bit to 0 once software reads CHx_SWHSDstReg.SWHS_Ack_Dst bit and sees it as 1. Software can only set this bit to 1; it is
not allowed to clear this bit to 0; only DW_axi_dmac can clear this bit.
Note: SWHS_Req_Dst bit is written only if the corresponding write enable bit, SWHS_Req_Dst_WE is asserted on the same register write operation and if the Channelx is enabled in the DMAC_ChEnReg register. This allows software to set a bit in the CHx_SWHSDstReg register without performing a read-modified write operation.

Value	Description
0x0	Destination peripheral is not requesting for a burst transfer
0x1	Destination peripheral request for a dma transfer

RW

0x0