CH3_INTSTATUS_ENABLEREG 

         Writing 1 to specific field enables the corresponding interrupt status generation in Channelx Interrupt Status Register(CH3_IntStatusReg).
Module Instance Base Address Register Address
i_dma__dmac1_ahb_slv__10dc0000__Channel3_Registers_Address_Block__SEG_L4_AHB_dmac1_s_0x0_0x10000 0x10DC0300 0x10DC0380

Size: 64

Offset: 0x80

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_32to63

RO 0x0

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_32to63

RO 0x0

Enable_ECC_PROT_UIDMem_UnCorrERR_IntStat

RO 0x0

Enable_ECC_PROT_UIDMem_CorrERR_IntStat

RO 0x0

Enable_ECC_PROT_CHMem_UnCorrERR_IntStat

RO 0x0

Enable_ECC_PROT_CHMem_CorrERR_IntStat

RO 0x0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Enable_CH_ABORTED_IntStat

RW 0x0

Enable_CH_DISABLED_IntStat

RW 0x0

Enable_CH_SUSPENDED_IntStat

RW 0x0

Enable_CH_SRC_SUSPENDED_IntStat

RW 0x0

Enable_CH_LOCK_CLEARED_IntStat

RW 0x0

RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_26

RO 0x0

Enable_SLVIF_WRPARITY_ERR_IntStat

RO 0x0

RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_22to24

RO 0x0

Enable_SLVIF_WRONHOLD_ERR_IntStat

RW 0x0

Enable_SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat

RW 0x0

Enable_SLVIF_WRONCHEN_ERR_IntStat

RW 0x0

Enable_SLVIF_RD2RWO_ERR_IntStat

RW 0x0

Enable_SLVIF_WR2RO_ERR_IntStat

RW 0x0

Enable_SLVIF_DEC_ERR_IntStat

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_15

RO 0x0

Enable_SLVIF_MULTIBLKTYPE_ERR_IntStat

RW 0x0

Enable_SHADOWREG_OR_LLI_INVALID_ERR_IntStat

RW 0x0

Enable_LLI_WR_SLV_ERR_IntStat

RW 0x0

Enable_LLI_RD_SLV_ERR_IntStat

RW 0x0

Enable_LLI_WR_DEC_ERR_IntStat

RW 0x0

Enable_LLI_RD_DEC_ERR_IntStat

RW 0x0

Enable_DST_SLV_ERR_IntStat

RW 0x0

Enable_SRC_SLV_ERR_IntStat

RW 0x0

Enable_DST_DEC_ERR_IntStat

RW 0x0

Enable_SRC_DEC_ERR_IntStat

RW 0x0

Enable_DST_TRANSCOMP_IntStat

RW 0x0

Enable_SRC_TRANSCOMP_IntStat

RW 0x0

RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_2

RO 0x0

Enable_DMA_TFR_DONE_IntStat

RW 0x0

Enable_BLOCK_TFR_DONE_IntStat

RW 0x0

CH3_INTSTATUS_ENABLEREG Fields

Bit Name Description Access Reset
63:36 RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_32to63 
DMAC Channelx Interrupt Status Enable Register (bits 32to63) Reserved bits - Read Only
 RO 0x0
35 Enable_ECC_PROT_UIDMem_UnCorrERR_IntStat 
Channel x Unique ID Memory Interface ECC Protection Uncorrectable Error Interrupt enable.
 - 0: Disable the generation of Channel x UID Memory Interface Uncorrectable Error Interrupt in CHx_INTSTATUSREG.
 - 1: Enable the generation Channel x UID Memory Interface Uncorrectable Error Interrupt in CHx_INTSTATUSREG.
Value Description
0x0 Disable the propagation of UID Memory ECC Uncorrectable error Interrupt in CH3_INTSTATUSREG
0x1 Enable the propagation of UID Memory ECC Uncorrectable error Interrupt in CH3_INTSTATUSREG
RO 0x0
34 Enable_ECC_PROT_UIDMem_CorrERR_IntStat 
Channel x Unique ID Memory Interface ECC Protection Correctable Error Interrupt enable.
 - 0: Disable the generation of Channel x UID Memory Interface Correctable Error Interrupt in CHx_INTSTATUSREG.
 - 1: Enable the generation Channel x UID Memory Interface Correctable Error Interrupt in CHx_INTSTATUSREG.
Value Description
0x0 Disable the propagation of UID Memory ECC Correctable error Interrupt in CH3_INTSTATUSREG
0x1 Enable the propagation of UID Memory ECC Correctable error Interrupt in CH3_INTSTATUSREG
RO 0x0
33 Enable_ECC_PROT_CHMem_UnCorrERR_IntStat 
Channel x Channel Memory Interface ECC Protection Uncorrectable Error Interrupt enable.
 - 0: Disable the generation of Channel x Channel Memory Interface Uncorrectable Error Interrupt in CHx_INTSTATUSREG.
 - 1: Enable the generation Channel x Channel Memory Interface Uncorrectable Error Interrupt in CHx_INTSTATUSREG.
Value Description
0x0 Disable the propagation of Channel Memory ECC Uncorrectable error Interrupt in CH3_INTSTATUSREG
0x1 Enable the propagation of Channel Memory ECC Uncorrectable error Interrupt in CH3_INTSTATUSREG
RO 0x0
32 Enable_ECC_PROT_CHMem_CorrERR_IntStat 
Channel x Channel Memory Interface ECC Protection Correctable Error Interrupt enable.
 - 0: Disable the generation of Channel x Channel Memory Interface Correctable Error Interrupt in CHx_INTSTATUSREG.
 - 1: Enable the generation of Channel x Channel Memory Interface Correctable Error Interrupt in CHx_INTSTATUSREG.
Value Description
0x0 Disable the propagation of Channel Memory ECC Correctable error Interrupt in CH3_INTSTATUSREG
0x1 Enable the propagation of Channel Memory ECC Correctable error Interrupt in CH3_INTSTATUSREG
RO 0x0
31 Enable_CH_ABORTED_IntStat 
Channel Aborted Status Enable.
 - 0: Disable the generation of Channel Aborted Interrupt in CHx_INTSTATUSREG
 - 1: Enable the generation of Channel Aborted Interrupt in CHx_INTSTATUSREG
Value Description
0x0 Disable the generation of Channel Aborted Interrupt in CH3_INTSTATUSREG
0x1 Enable the generation of Channel Aborted Interrupt in CH3_INTSTATUSREG
RW 0x0
30 Enable_CH_DISABLED_IntStat 
Channel Disabled Status Enable.
 - 0: Disable the generation of Channel Disabled Interrupt in CHx_INTSTATUSREG
 - 1: Enable the generation of Channel Disabled Interrupt in CHx_INTSTATUSREG
Value Description
0x0 Disable the generation of Channel Disabled Interrupt in CH3_INTSTATUSREG
0x1 Enable the generation of Channel Disabled Interrupt in CH3_INTSTATUSREG
RW 0x0
29 Enable_CH_SUSPENDED_IntStat 
Channel Suspended Status Enable.
 - 0: Disable the generation of Channel Suspended Interrupt in CHx_INTSTATUSREG
 - 1: Enable the generation of Channel Suspended Interrupt in CHx_INTSTATUSREG
Value Description
0x0 Disable the generation of Channel Suspended Interrupt in CH3_INTSTATUSREG
0x1 Enable the generation of Channel Suspended Interrupt in CH3_INTSTATUSREG
RW 0x0
28 Enable_CH_SRC_SUSPENDED_IntStat 
Channel Source Suspended Status Enable.
 - 0: Disable the generation of Channel Source Suspended Interrupt in CHx_INTSTATUSREG
 - 1: Enable the generation of Channel Source Suspended Interrupt in CHx_INTSTATUSREG
Value Description
0x0 Disable the generation of Channel Source Suspended Interrupt in CH3_INTSTATUSREG
0x1 Enable the generation of Channel Source Suspended Interrupt in CH3_INTSTATUSREG
RW 0x0
27 Enable_CH_LOCK_CLEARED_IntStat 
Channel Lock Cleared Status Enable.
 - 0: Disable the generation of Channel LOCK CLEARED Interrupt in CHx_INTSTATUSREG
 - 1: Enable the generation of Channel LOCK CLEARED Interrupt in CHx_INTSTATUSREG
Value Description
0x0 Disable the generation of Channel LOCK CLEARED Interrupt in CH3_INTSTATUSREG
0x1 Enable the generation of Channel LOCK CLEARED Interrupt in CH3_INTSTATUSREG
RW 0x0
26 RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_26 
DMAC Channelx Interrupt Status Register (bit 26) Reserved bit - Read Only
 RO 0x0
25 Enable_SLVIF_WRPARITY_ERR_IntStat 
Slave Interface Write Parity Error Enable.
 - 0: Disable the generation of Slave Interface Write Parity Error Interrupt in CHx_INTSTATUSREG
 - 1: Enable the generation of Slave Interface Write Parity Error Interrupt in CHx_INTSTATUSREG
Value Description
0x0 Disable the generation of Slave Interface Write Parity Error in CH3_INTSTATUSREG
0x1 Enable the generation of Slave Interface Write Parity Error in CH3_INTSTATUSREG
RO 0x0
24:22 RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_22to24 
DMAC Channelx Interrupt Status Register (bits 22to24) Reserved bits - Read Only
 RO 0x0
21 Enable_SLVIF_WRONHOLD_ERR_IntStat 
Slave Interface Write On Hold Error Status Enable.
 - 0: Disable the generation of Slave Interface Write On Hold Error Interrupt in CHx_INTSTATUSREG
 - 1: Enable the generation of Slave Interface Write On Hold Error Interrupt in CHx_INTSTATUSREG
Value Description
0x0 Disable the generation of Slave Interface Write On Hold Error Interrupt in CH3_INTSTATUSREG
0x1 Enable the generation of Slave Interface Write On Hold Error Interrupt in CH3_INTSTATUSREG
RW 0x0
20 Enable_SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat 
Shadow Register Write On Valid Error Status Enable.
 - 0: Disable the generation of Shadow Register Write On Valid Error Interrupt in CHx_INTSTATUSREG
 - 1: Enable the generation of Shadow register Write On Valid Error Interrupt in CHx_INTSTATUSREG
Value Description
0x0 Disable the generation of Shadow Register Write On Valid Error Interrupt in CH3_INTSTATUSREG
0x1 Enable the generation of Shadow register Write On Valid Error Interrupt in CH3_INTSTATUSREG
RW 0x0
19 Enable_SLVIF_WRONCHEN_ERR_IntStat 
Slave Interface Write On Channel Enabled Error Status Enable.
 - 0: Disable the generation of Slave Interface Write On Channel enabled Error Interrupt in CHx_INTSTATUSREG
 - 1: Enable the generation of Slave Interface Write On Channel enabled Error Interrupt in CHx_INTSTATUSREG
Value Description
0x0 Disable the generation of Slave Interface Write On Channel enabled Error Interrupt in CH3_INTSTATUSREG
0x1 Enable the generation of Slave Interface Write On Channel enabled Error Interrupt in CH3_INTSTATUSREG
RW 0x0
18 Enable_SLVIF_RD2RWO_ERR_IntStat 
Slave Interface Read to write Only Error Status Enable.
 - 0: Disable the generation of Slave Interface Read to Write only Error Interrupt in CHx_INTSTATUSREG
 - 1: Enable the generation of Slave Interface Read to Write Only Error Interrupt in CHx_INTSTATUSREG
Value Description
0x0 Disable the generation of Slave Interface Read to Write only Error Interrupt in CH3_INTSTATUSREG
0x1 Enable the generation of Slave Interface Read to Write Only Error Interrupt in CH3_INTSTATUSREG
RW 0x0
17 Enable_SLVIF_WR2RO_ERR_IntStat 
Slave Interface Write to Read Only Error Status Enable.
 - 0: Disable the generation of Slave Interface Write to Read only Error Interrupt in CHx_INTSTATUSREG
 - 1: Enable the generation of Slave Interface Write to Read Only Error Interrupt in CHx_INTSTATUSREG
Value Description
0x0 Disable the generation of Slave Interface Write to Read only Error Interrupt in CH3_INTSTATUSREG
0x1 Enable the generation of Slave Interface Write to Read Only Error Interrupt in CH3_INTSTATUSREG
RW 0x0
16 Enable_SLVIF_DEC_ERR_IntStat 
Slave Interface Decode Error Status Enable.
 - 0: Disable the generation of Slave Interface Decode Error Interrupt in CHx_INTSTATUSREG
 - 1: Enable the generation of Slave Interface Decode Error Interrupt in CHx_INTSTATUSREG
Value Description
0x0 Disable the generation of Slave Interface Decode Error Interrupt in CH3_INTSTATUSREG
0x1 Enable the generation of Slave Interface Decode Error Interrupt in CH3_INTSTATUSREG
RW 0x0
15 RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_15 
DMAC Channelx Interrupt Status Register (bit 15) Reserved bit - Read Only
 RO 0x0
14 Enable_SLVIF_MULTIBLKTYPE_ERR_IntStat 
Slave Interface Multi Block type Error Status Enable.
 - 0: Disable the generation of Slave Interface Multi Block type Error Interrupt in CHx_INTSTATUSREG
 - 1: Enable the generation of Slave Interface Multi Block type Error Interrupt in CHx_INTSTATUSREG
Value Description
0x0 Disable the generation of Slave Interface Multi Block type Error Interrupt in CH3_INTSTATUSREG
0x1 Enable the generation of Slave Interface Multi Block type Error Interrupt in CH3_INTSTATUSREG
RW 0x0
13 Enable_SHADOWREG_OR_LLI_INVALID_ERR_IntStat 
Shadow register or LLI Invalid Error Status Enable.
 - 0: Disable the generation of Shadow Register or LLI Invalid Error Interrupt in CHx_INTSTATUSREG
 - 1: Enable the generation of Shadow Register or LLI Invalid  Error Interrupt in CHx_INTSTATUSREG
Value Description
0x0 Disable the generation of Shadow Register or LLI Invalid Error Interrupt in CH3_INTSTATUSREG
0x1 Enable the generation of Shadow Register or LLI Invalid Error Interrupt in CH3_INTSTATUSREG
RW 0x0
12 Enable_LLI_WR_SLV_ERR_IntStat 
LLI WRITE Slave Error Status Enable.
 - 0: Disable the generation of LLI WRITE Slave Error Interrupt in CHx_INTSTATUSREG
 - 1: Enable the generation of LLI WRITE Slave Error Interrupt in CHx_INTSTATUSREG
Value Description
0x0 Disable the generation of LLI WRITE Slave Error Interrupt in CH3_INTSTATUSREG
0x1 Enable the generation of LLI WRITE Slave Error Interrupt in CH3_INTSTATUSREG
RW 0x0
11 Enable_LLI_RD_SLV_ERR_IntStat 
LLI Read Slave Error Status Enable.
 - 0: Disable the generation of LLI Read Slave Error Interrupt in CHx_INTSTATUSREG
 - 1: Enable the generation of LLI Read Slave Error Interrupt in CHx_INTSTATUSREG
Value Description
0x0 Disable the generation of LLI Read Slave Error Interrupt in CH3_INTSTATUSREG
0x1 Enable the generation of LLI Read Slave Error Interrupt in CH3_INTSTATUSREG
RW 0x0
10 Enable_LLI_WR_DEC_ERR_IntStat 
LLI WRITE Decode Error Status Enable.
 - 0: Disable the generation of LLI WRITE Decode Error Interrupt in CHx_INTSTATUSREG
 - 1: Enable the generation of LLI WRITE Decode Error Interrupt in CHx_INTSTATUSREG
Value Description
0x0 Disable the generation of LLI WRITE Decode Error Interrupt in CH3_INTSTATUSREG
0x1 Enable the generation of LLI WRITE Decode Error Interrupt in CH3_INTSTATUSREG
RW 0x0
9 Enable_LLI_RD_DEC_ERR_IntStat 
LLI Read Decode Error Status Enable.
 - 0: Disable the generation of LLI Read Decode Error Interrupt in CHx_INTSTATUSREG
 - 1: Enable the generation of LLI Read Decode Error Interrupt in CHx_INTSTATUSREG
Value Description
0x0 Disable the generation of LLI Read Decode Error Interrupt in CH3_INTSTATUSREG
0x1 Enable the generation of LLI Read Decode Error Interrupt in CH3_INTSTATUSREG
RW 0x0
8 Enable_DST_SLV_ERR_IntStat 
Destination Slave Error Status Enable.
 - 0: Disable the generation of Destination Slave Error Interrupt in CHx_INTSTATUSREG
 - 1: Enable the generation of Destination Slave Error Interrupt in CHx_INTSTATUSREG
Value Description
0x0 Disable the generation of Destination Slave Error Interrupt in CH3_INTSTATUSREG
0x1 Enable the generation of Destination Slave Error Interrupt in CH3_INTSTATUSREG
RW 0x0
7 Enable_SRC_SLV_ERR_IntStat 
Source Slave Error Status Enable.
 - 0: Disable the generation of Source Slave Error Interrupt in CHx_INTSTATUSREG
 - 1: Enable the generation of Source Slave Error Interrupt in CHx_INTSTATUSREG
Value Description
0x0 Disable the generation of Source Slave Error Interrupt in CH3_INTSTATUSREG
0x1 Enable the generation of Source Slave Error Interrupt in CH3_INTSTATUSREG
RW 0x0
6 Enable_DST_DEC_ERR_IntStat 
Destination Decode Error Status Enable.
 - 0: Disable the generation of Destination Decode Error Interrupt in CHx_INTSTATUSREG
 - 1: Enable the generation of Destination Decode Error Interrupt in CHx_INTSTATUSREG
Value Description
0x0 Disable the generation of Destination Decode Error Interrupt in CH3_INTSTATUSREG
0x1 Enable the generation of Destination Decode Error Interrupt in CH3_INTSTATUSREG
RW 0x0
5 Enable_SRC_DEC_ERR_IntStat 
Source Decode Error Status Enable.
 - 0: Disable the generation of Source Decode Error Interrupt in CHx_INTSTATUSREG
 - 1: Enable the generation of Source Decode Error Interrupt in CHx_INTSTATUSREG
Value Description
0x0 Disable the generation of Source Decode Error Interrupt in CH3_INTSTATUSREG
0x1 Enable the generation of Source Decode Error Interrupt in CH3_INTSTATUSREG
RW 0x0
4 Enable_DST_TRANSCOMP_IntStat 
Destination Transaction Completed Status Enable.
 - 0: Disable the generation of Destination Transaction complete Interrupt in CHx_INTSTATUSREG
 - 1: Enable the generation of Destination Transaction complete Interrupt in CHx_INTSTATUSREG
Value Description
0x0 Disable the generation of Destination Transaction complete Interrupt in CH3_INTSTATUSREG
0x1 Enable the generation of Destination Transaction complete Interrupt in CH3_INTSTATUSREG
RW 0x0
3 Enable_SRC_TRANSCOMP_IntStat 
Source Transaction Completed Status Enable.
 - 0: Disable the generation of Source Transaction Complete Interrupt in CHx_INTSTATUSREG
 - 1: Enable the generation of Source Transaction Complete Interrupt in CHx_INTSTATUSREG
Value Description
0x0 Disable the generation of Source Transaction Complete Interrupt in CH3_INTSTATUSREG
0x1 Enable the generation of Source Transaction Complete Interrupt in CH3_INTSTATUSREG
RW 0x0
2 RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_2 
DMAC Channelx Interrupt Status Register (bit 2) Reserved bit - Read Only
 RO 0x0
1 Enable_DMA_TFR_DONE_IntStat 
DMA Transfer Done Interrupt Status Enable.
 - 0: Disable the generation of DMA Transfer Done Interrupt in CHx_INTSTATUSREG
 - 1: Enable the generation of DMA Transfer Done Interrupt in CHx_INTSTATUSREG
Value Description
0x0 Disable the generation of DMA Transfer Done Interrupt in CH3_INTSTATUSREG
0x1 Enable the generation of DMA Transfer Done Interrupt in CH3_INTSTATUSREG
RW 0x0
0 Enable_BLOCK_TFR_DONE_IntStat 
Block Transfer Done Interrupt Status Enable.
 - 0: Disable the generation of Block Transfer Done Interrupt in CHx_INTSTATUSREG
 - 1: Enable the generation of Block Transfer Done Interrupt in CHx_INTSTATUSREG
Value Description
0x0 Disable the generation of Block Transfer Done Interrupt in CH3_INTSTATUSREG
0x1 Enable the generation of Block Transfer Done Interrupt in CH3_INTSTATUSREG
RW 0x0