CH3_INTSTATUS 

         Channelx Interrupt Status Register captures the Channelx specific interrupts
Module Instance Base Address Register Address
i_dma__dmac1_ahb_slv__10dc0000__Channel3_Registers_Address_Block__SEG_L4_AHB_dmac1_s_0x0_0x10000 0x10DC0300 0x10DC0388

Size: 64

Offset: 0x88

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

RSVD_DMAC_CHx_INTSTATUSREG_36to63

RO 0x0

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD_DMAC_CHx_INTSTATUSREG_36to63

RO 0x0

ECC_PROT_UIDMem_UnCorrERR_IntStat

RO 0x0

ECC_PROT_UIDMem_CorrERR_IntStat

RO 0x0

ECC_PROT_CHMem_UnCorrERR_IntStat

RO 0x0

ECC_PROT_CHMem_CorrERR_IntStat

RO 0x0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CH_ABORTED_IntStat

RO 0x0

CH_DISABLED_IntStat

RO 0x0

CH_SUSPENDED_IntStat

RO 0x0

CH_SRC_SUSPENDED_IntStat

RO 0x0

CH_LOCK_CLEARED_IntStat

RO 0x0

RSVD_DMAC_CHx_INTSTATUSREG_26

RO 0x0

SLVIF_WRPARITY_ERR_IntStat

RO 0x0

RSVD_DMAC_CHx_INTSTATUSREG_22to24

RO 0x0

SLVIF_WRONHOLD_ERR_IntStat

RO 0x0

SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat

RO 0x0

SLVIF_WRONCHEN_ERR_IntStat

RO 0x0

SLVIF_RD2RWO_ERR_IntStat

RO 0x0

SLVIF_WR2RO_ERR_IntStat

RO 0x0

SLVIF_DEC_ERR_IntStat

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD_DMAC_CHx_INTSTATUSREG_15

RO 0x0

SLVIF_MULTIBLKTYPE_ERR_IntStat

RO 0x0

SHADOWREG_OR_LLI_INVALID_ERR_IntStat

RO 0x0

LLI_WR_SLV_ERR_IntStat

RO 0x0

LLI_RD_SLV_ERR_IntStat

RO 0x0

LLI_WR_DEC_ERR_IntStat

RO 0x0

LLI_RD_DEC_ERR_IntStat

RO 0x0

DST_SLV_ERR_IntStat

RO 0x0

SRC_SLV_ERR_IntStat

RO 0x0

DST_DEC_ERR_IntStat

RO 0x0

SRC_DEC_ERR_IntStat

RO 0x0

DST_TRANSCOMP_IntStat

RO 0x0

SRC_TRANSCOMP_IntStat

RO 0x0

RSVD_DMAC_CHx_INTSTATUSREG_2

RO 0x0

DMA_TFR_DONE_IntStat

RO 0x0

BLOCK_TFR_DONE_IntStat

RO 0x0

CH3_INTSTATUS Fields

Bit Name Description Access Reset
63:36 RSVD_DMAC_CHx_INTSTATUSREG_36to63 
DMAC Channelx Specific Interrupt Register (bits 36to63) Reserved bits - Read Only
 RO 0x0
35 ECC_PROT_UIDMem_UnCorrERR_IntStat 
Channel x UID Memory Interface ECC Protection related Uncorrectable Error Interrupt Status bit.

This error occurs if ECC Uncorrectable error is detected on the UID Memory Interface data. 

 - 0: No Channel x UID Memory Interface Uncorrectable Error.
 - 1: Channel x UID Memory Interface Uncorrectable Error detected. 

Error Interrupt status is generated if the corresponding Status Enable bit in CHx_INTSTATUS_ENABLEReg register is set to 1. This bit is cleared to 0 on writing 1 to the corresponding interrupt clear bit in CHx_IntClearReg.
Value Description
0x0 Channel x UID Memory Interface Uncorrectable Error not detected
0x1 Channel x UID Memory Interface Uncorrectable Error detected
RO 0x0
34 ECC_PROT_UIDMem_CorrERR_IntStat 
Channel x UID Memory Interface ECC Protection related Correctable Error Interrupt Status bit.

This error occurs if ECC correctable error is detected on the UID Memory Interface data. 

 - 0: No Channel x UID Memory Interface correctable Error.
 - 1: Channel x UID Memory Interface correctable Error detected. 

Error Interrupt status is generated if the corresponding Status Enable bit in CHx_INTSTATUS_ENABLEReg register is set to 1. This bit is cleared to 0 on writing 1 to the corresponding interrupt clear bit in CHx_IntClearReg.
Value Description
0x0 Channel x UID Memory Interface correctable Error not detected
0x1 Channel x UID Memory Interface correctable Error detected
RO 0x0
33 ECC_PROT_CHMem_UnCorrERR_IntStat 
Channel x FIFO Memory Interface ECC Protection related Uncorrectable Error Interrupt Status bit.

This error occurs if ECC Uncorrectable error is detected on the FIFO Memory Interface data. 

 - 0: No Channel x FIFO Memory Interface Uncorrectable Error.
 - 1: Channel x FIFO Memory Interface Uncorrectable Error detected. 

Error Interrupt status is generated if the corresponding Status Enable bit in CHx_INTSTATUS_ENABLEReg register is set to 1. This bit is cleared to 0 on writing 1 to the corresponding interrupt clear bit in CHx_IntClearReg.
Value Description
0x0 Channel x FIFO Memory Interface Uncorrectable Error not detected
0x1 Channel x FIFO Memory Interface Uncorrectable Error detected
RO 0x0
32 ECC_PROT_CHMem_CorrERR_IntStat 
Channel x FIFO Memory Interface ECC Protection related Correctable Error Interrupt Status bit.

This error occurs if ECC correctable error is detected on the FIFO Memory Interface data. 

 - 0: No Channel x FIFO Memory Interface correctable Error.
 - 1: Channel x FIFO Memory Interface correctable Error detected. 

Error Interrupt status is generated if the corresponding Status Enable bit in CHx_INTSTATUS_ENABLEReg register is set to 1. This bit is cleared to 0 on writing 1 to the corresponding interrupt clear bit in CHx_IntClearReg.
Value Description
0x0 Channel x FIFO Memory Interface correctable Error not detected
0x1 Channel x FIFO Memory Interface correctable Error detected
RO 0x0
31 CH_ABORTED_IntStat 
Channel Aborted.
This indicates to the software that the corresponding channel in DW_axi_dmac is aborted.
 - 0: Channel is not aborted
 - 1: Channel is aborted

Error Interrupt is generated if the corresponding bit in CHx_INTSTATUS_ENABLEReg is enabled. This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in CHx_IntClearReg register.
Value Description
0x0 Channel is not aborted
0x1 Channel is aborted
RO 0x0
30 CH_DISABLED_IntStat 
Channel Disabled.
This indicates to the software that the corresponding channel in DW_axi_dmac is disabled.
 - 0: Channel is not disabled.
 - 1: Channel is disabled.
    Error Interrupt is generated if the corresponding bit in CHx_INTSTATUS_ENABLEReg is enabled.

    This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in CHx_IntClearReg register.
Value Description
0x0 Channel is not disabled
0x1 Channel is disabled
RO 0x0
29 CH_SUSPENDED_IntStat 
Channel Suspended.
This indicates to the software that the corresponding channel in DW_axi_dmac is suspended.
 - 0: Channel is not suspended.
 - 1: Channel is suspended.

Error Interrupt is generated if the corresponding bit in CHx_INTSTATUS_ENABLEReg is enabled. This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in CHx_IntClearReg register.
Value Description
0x0 Channel is not suspended
0x1 Channel is suspended
RO 0x0
28 CH_SRC_SUSPENDED_IntStat 
Channel Source Suspended.
This indicates to the software that the corresponding channel source data transfer in DW_axi_dmac is suspended.
 - 0: Channel source is not suspended
 - 1: Channel Source is suspended.

Error Interrupt is generated if the corresponding bit in CHx_INTSTATUS_ENABLEReg is enabled. This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in CHx_IntClearReg register.
Value Description
0x0 Channel source is not suspended
0x1 Channel Source is suspended
RO 0x0
27 CH_LOCK_CLEARED_IntStat 
Channel Lock Cleared.
This indicates to the software that the locking of the corresponding channel in DW_axi_dmac is cleared.
 - 0: Channel locking is not cleared.
 - 1: Channel locking is cleared.

Channel locking is cleared by DW_axi_dmac during the following situations:
 - Channel locking is cleared and the channel locking settings in CHx_CFG register is reset if DW_axi_dmac disables the channel upon request from software.
 - Channel locking is cleared and the channel locking settings in CHx_CFG register is reset if DW_axi_dmac disables the channel upon receiving error response on the master interface.

This bit is cleared to 0 on enabling the channel.
Value Description
0x0 Channel locking is not cleared, if present.
0x1 Channel Locking is cleared
RO 0x0
26 RSVD_DMAC_CHx_INTSTATUSREG_26 
DMAC Channelx Specific Interrupt Register (bit 26) Reserved bit - Read Only
 RO 0x0
25 SLVIF_WRPARITY_ERR_IntStat 
Slave Interface Write Parity Error.
This error occurs if a Write operation is performed on a channel register; But the Write data fails the even/odd parity check.
 - 0: No Slave Interface Write Parity Errors.
 - 1: Slave Interface Write Parity Error detected.

Error Interrupt is generated if the corresponding bit in CHx_INTSTATUS_ENABLEReg is enabled. This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in CHx_IntClearReg register.
Value Description
0x0 No Slave Interface Write Parity Errors
0x1 Slave Interface Write Parity Error detected
RO 0x0
24:22 RSVD_DMAC_CHx_INTSTATUSREG_22to24 
DMAC Channelx Specific Interrupt Register (bits 22to24) Reserved bits - Read Only
 RO 0x0
21 SLVIF_WRONHOLD_ERR_IntStat 
Slave Interface Write On Hold Error.
This error occurs if an illegal write operation is performed on a register; this happens if a write operation is performed on a channel register when DW_axi_dmac is in Hold mode.
 - 0: No Slave Interface Write On Hold Errors.
 - 1: Slave Interface Write On Hold Error detected.

Error Interrupt is generated if the corresponding bit in CHx_INTSTATUS_ENABLEReg is enabled. This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in CHx_IntClearReg register.
Value Description
0x0 No Slave Interface Write On Hold Errors
0x1 Slave Interface Write On Hold Error detected
RO 0x0
20 SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat 
Shadow Register Write On Valid Error.
This error occurs if shadow register based multi-block transfer is enabled and software tries to write to the shadow register when CHx_CTL.ShadowReg_Or_LLI_Valid bit is 1.
 - 0: No Slave Interface Shadow Register Write On Valid Errors.
 - 1: Slave Interface Shadow Register Write On Valid Error detected.

Error Interrupt is generated if the corresponding bit in CHx_INTSTATUS_ENABLEReg is enabled. This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in CHx_IntClearReg register.
Value Description
0x0 No Slave Interface Shadow Register Write On Valid Errors
0x1 Slave Interface Shadow Register Write On Valid Error detected
RO 0x0
19 SLVIF_WRONCHEN_ERR_IntStat 
Slave Interface Write On Channel Enabled Error.
This error occurs if an illegal write operation is performed on a register; this happens if a write operation is performed on a register when the channel is enabled and if it is not allowed for the corresponding register as per the DW_axi_dmac specification.
 - 0: No Slave Interface Write On Channel Enabled Errors.
 - 1: Slave Interface Write On Channel Enabled Error detected.

Error Interrupt is generated if the corresponding bit in CHx_INTSTATUS_ENABLEReg is enabled. This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in CHx_IntClearReg register.
Value Description
0x0 No Slave Interface Write On Channel Enabled Errors
0x1 Slave Interface Write On Channel Enabled Error detected
RO 0x0
18 SLVIF_RD2RWO_ERR_IntStat 
Slave Interface Read to write Only Error.
This error occurs if read operation is performed to a Write Only register.
 - 0: No Slave Interface Read to Write Only Errors.
 - 1: Slave Interface Read to Write Only Error detected.

Error Interrupt is generated if the corresponding bit in CHx_INTSTATUS_ENABLEReg is enabled. This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in CHx_IntClearReg register.
Value Description
0x0 No Slave Interface Read to Write Only Errors
0x1 Slave Interface Read to Write Only Error detected
RO 0x0
17 SLVIF_WR2RO_ERR_IntStat 
Slave Interface Write to Read Only Error.
This error occurs if write operation is performed to a Read Only register.
 - 0: No Slave Interface Write to Read Only Errors.
 - 1: Slave Interface Write to Read Only Error detected.

Error Interrupt is generated if the corresponding bit in CHx_INTSTATUS_ENABLEReg is enabled. This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in CHx_IntClearReg register.
Value Description
0x0 No Slave Interface Write to Read Only Errors
0x1 Slave Interface Write to Read Only Error detected
RO 0x0
16 SLVIF_DEC_ERR_IntStat 
Slave Interface Decode Error.
Decode Error generated by DW_axi_dmac during register access. This error occurs if the register access is to invalid address in Channelx register space resulting in error response by DW_axi_dmac slave interface.
 - 0: No Slave Interface Decode errors.
 - 1: Slave Interface Decode Error detected.

Error Interrupt is generated if the corresponding bit in CHxINTSTATUS_ENABLEReg is enabled. This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in CHx_IntClearReg register.
Value Description
0x0 No Slave Interface Decode errors
0x1 Slave Interface Decode Error detected
RO 0x0
15 RSVD_DMAC_CHx_INTSTATUSREG_15 
DMAC Channelx Specific Interrupt Register (bit 15) Reserved bit - Read Only
 RO 0x0
14 SLVIF_MULTIBLKTYPE_ERR_IntStat 
Slave Interface Multi Block type Error.
This error occurs if multi-block transfer type programmed in CHx_CFG register (SRC_MLTBLK_TYPE and DST_MLTBLK_TYPE) is invalid. This error condition causes the DW_axi_dmac to halt the corresponding channel gracefully; Error Interrupt is generated if the corresponding channel error interrupt mask bit is set to 0 and the channel waits till software writes (any value) to CHx_BLK_TFR_ResumeReqReg to indicate valid multi-block transfer type availability.
 - 0: No Multi-block transfer type Errors.
 - 1: Multi-block transfer type Error detected.

Error Interrupt is generated if the corresponding bit in CHx_INTSTATUS_ENABLEReg is enabled. This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in CHx_IntClearReg register.
Value Description
0x0 No Multi-block transfer type Errors
0x1 Multi-block transfer type Error detected
RO 0x0
13 SHADOWREG_OR_LLI_INVALID_ERR_IntStat 
Shadow register or LLI Invalid Error.
This error occurs if CHx_CTL.ShadowReg_Or_LLI_Valid bit is seen to be 0 during DW_axi_dmac Shadow
Register / LLI fetch phase. This error condition causes the DW_axi_dmac to halt the corresponding channel gracefully; Error Interrupt is generated if the corresponding channel error interrupt mask bit
is set to 0 and the channel waits till software writes (any value) to CHx_BLK_TFR_ResumeReqReg to indicate valid Shadow Register availability.
In the case of LLI pre-fetching, ShadowReg_Or_LLI_Invalid_ERR Interrupt is not generated even if ShadowReg_Or_LLI_Valid bit is seen to be 0 for the pre-fetched LLI. In this case, DW_axi_dmac re-attempts the LLI fetch operation after completing the current block transfer and generates ShadowReg_Or_LLI_Invalid_ERR Interrupt only if ShadowReg_Or_LLI_Valid bit is still seen to be 0.
 - 0: No Shadow Register / LLI Invalid errors.
 - 1: Shadow Register / LLI Invalid error detected.

Error Interrupt is generated if the corresponding bit in CHx_INTSTATUS_ENABLEReg is enabled. This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in CHx_IntClearReg register.
Value Description
0x0 No Shadow Register / LLI Invalid errors
0x1 Shadow Register / LLI Invalid error detected
RO 0x0
12 LLI_WR_SLV_ERR_IntStat 
LLI WRITE Slave Error.
Slave Error detected by Master Interface during LLI write-back operation. This error occurs if the slave interface on which LLI resides issues a Slave Error. This error condition causes the DW_axi_dmac to disable the corresponding channel gracefully; the DMAC_ChEnReg.CH_EN3 bit which received the error is set to 0.
 - 0: No LLI write Slave Errors.
 - 1: LLI Write SLAVE Error detected.

Error Interrupt is generated if the corresponding bit in CHx_INTSTATUS_ENABLEReg is enabled. This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in CHx_IntClearReg register.
Value Description
0x0 No LLI write Slave Errors
0x1 LLI Write SLAVE Error detected
RO 0x0
11 LLI_RD_SLV_ERR_IntStat 
LLI Read Slave Error.
Slave Error detected by Master Interface during LLI read operation. This error occurs if the slave interface on which LLI resides issues a Slave Error. This error condition causes the DW_axi_dmac to disable the corresponding channel gracefully; the DMAC_ChEnReg.CH_EN3 bit which received the error is set to 0.
 - 0: No LLI Read Slave Errors.
 - 1: LLI read Slave Error detected.

Error Interrupt is generated if the corresponding bit in CHx_INTSTATUS_ENABLEReg is enabled. This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in CHx_IntClearReg register.
Value Description
0x0 No LLI Read Slave Errors
0x1 LLI read Slave Error detected
RO 0x0
10 LLI_WR_DEC_ERR_IntStat 
LLI WRITE Decode Error.
Decode Error detected by Master Interface during LLI write-back operation. This error occurs if the access is to invalid address and a Decode Error is returned from interconnect/slave. This error condition causes the DW_axi_dmac to disable the corresponding channel gracefully; the DMAC_ChEnReg.CH_EN3 bit which received the error is set to 0.
 - 0: NO LLI Write Decode Errors.
 - 1: LLI write Decode Error detected.

Error Interrupt is generated if the corresponding bit in CHx_INTSTATUS_ENABLEReg is enabled. This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in CHx_IntClearReg register.
Value Description
0x0 NO LLI Write Decode Errors
0x1 LLI write Decode Error detected
RO 0x0
9 LLI_RD_DEC_ERR_IntStat 
LLI Read Decode Error.
Decode Error detected by Master Interface during LLI read operation. This error occurs if the access is to invalid address and a Decode Error is returned from interconnect/slave. This error condition causes the DW_axi_dmac to disable the corresponding channel gracefully; the DMAC_ChEnReg.CH_EN3 bit which received the error is set to 0.
 - 0: NO LLI Read Decode Errors.
 - 1: LLI Read Decode Error detected

Error Interrupt is generated if the corresponding bit in CHx_INTSTATUS_ENABLEReg is enabled.

    This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in CHx_IntClearReg register.
Value Description
0x0 NO LLI Read Decode Errors
0x1 LLI Read Decode Error detected
RO 0x0
8 DST_SLV_ERR_IntStat 
Destination Slave Error.
Slave Error detected by Master Interface during destination data transfer. This error occurs if the slave interface to which the data is written issues a Slave Error. This error condition causes the DW_axi_dmac to disable the corresponding channel gracefully; the DMAC_ChEnReg.CH_EN bit corresponding to the channel which received the error is set to 0.
 - 0: No Destination Slave Errors
 - 1: Destination Slave Errors Detected

This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in CHx_IntClearReg register.
Value Description
0x0 No Destination Slave Errors
0x1 Destination Slave Errors Detected
RO 0x0
7 SRC_SLV_ERR_IntStat 
Source Slave Error.
Slave Error detected by Master Interface during source data transfer. This error occurs if the slave interface from which the data is read issues a Slave Error. This error condition causes the DW_axi_dmac to disable the corresponding channel gracefully; the DMAC_ChEnReg.CH_EN bit corresponding to the channel which received the error is set to 0. 
 - 0: No Source Slave Errors
 - 1: Source Slave Error Detected

This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in CHx_IntClearReg register.
Value Description
0x0 No Source Slave Errors
0x1 Source Slave Error Detected
RO 0x0
6 DST_DEC_ERR_IntStat 
Destination Decode Error.
Decode Error detected by Master Interface during destination data transfer. This error occurs if the access is to invalid address and a Decode Error is returned from interconnect/slave. This error condition causes the DW_axi_dmac to disable the corresponding channel gracefully; the DMAC_ChEnReg.CH_EN bit corresponding to the channel which received the error is set to 0.
 - 0: No destination Decode Errors.
 - 1: Destination Decode Error Detected

This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in CHx_IntClearReg register.
Value Description
0x0 No destination Decode Errors.
0x1 Destination Decode Error Detected
RO 0x0
5 SRC_DEC_ERR_IntStat 
Source Decode Error.
Decode Error detected by Master Interface during source data transfer. This error occurs if the access is to invalid address and a Decode Error is returned from interconnect/slave. This error condition causes the DW_axi_dmac to disable the corresponding channel gracefully; the DMAC_ChEnReg.CH_EN bit corresponding to the channel which received the error is set to 0.
 - 0: No Source Decode Errors.
 - 1: Source Decode Error detected.

This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in CHx_IntClearReg register.
Value Description
0x0 No Source Decode Errors
0x1 Source Decode Error detected
RO 0x0
4 DST_TRANSCOMP_IntStat 
Destination Transaction Completed.

    This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in CHx_IntClearReg register or on enabling the channel (needed when interrupt is not enabled.
Value Description
0x0 Destination transaction is not complete
0x1 Destination transaction is complete
RO 0x0
3 SRC_TRANSCOMP_IntStat 
Source Transaction Completed.

    This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in CHx_IntClearReg register or on enabling the channel (needed when interrupt is not enabled.
Value Description
0x0 Source transation is not complete
0x1 Source transaction is complete
RO 0x0
2 RSVD_DMAC_CHx_INTSTATUSREG_2 
DMAC Channelx Specific Interrupt Register (bit 2) Reserved bit - Read Only
 RO 0x0
1 DMA_TFR_DONE_IntStat 
DMA Transfer Done.
This indicates to the software that the DW_axi_dmac has completed the requested DMA transfer.
The DW_axi_dmac sets this
bit to 1 along with setting CHx_INTSTATUS.BLOCK_TFR_DONE bit to 1 when the last block transfer is completed.
 - 0: DMA Transfer not completed.
 - 1: DMA Transfer Completed

This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in CHx_IntClearReg register.
Value Description
0x0 DMA Transfer not complete
0x1 DMA Transfer completed
RO 0x0
0 BLOCK_TFR_DONE_IntStat 
Block Transfer Done.
This indicates to the software that the DW_axi_dmac has completed the requested block transfer.
The DW_axi_dmac sets this bit to 1 when the transfer is successfully completed.
 - 0: Block Transfer not completed.
 - 1: Block Transfer completed.
This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in CHx_IntClearReg register.
Value Description
0x0 Block Transfer not complete
0x1 Block Transfer completed
RO 0x0